Datasheet IRFP4468PbF Datasheet

PD -97134

)

IRFP4468PbF

HEXFET® Power MOSFET

Applications

l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

G

D

V

DSS

R

DS(on

max. I

D

(Silicon Limited)

I

S

D

(Package Limited)

D

typ.

SOA

l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free

S

D

G

TO-247AC

GDS

Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

@ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

I

D

@ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited)

I

D

I

DM

@TC = 25°C

P

D

V

GS

dv/dt T

J

T

STG

Pulsed Drain Current

Maximum Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Peak Diode Recovery

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Mounting torque, 6-32 or M3 screw

d

f

Max.

c

290

200

195

1120

520

3.4

± 20

10

-55 to + 175

300

10lbxin (1.1Nxm)

100V

2.0m

2.6m

290A

195A

W/°C

V/ns

: :

c

A

W

V

°C

Avalanche Characteristics

g

e

740

See Fig. 14, 15, 22a, 22b,

mJ

E

AS (Thermally limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

d

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

Junction-to-Case

Case-to-Sink, Flat Greased Surface

Junction-to-Ambient

k –––

0.24 ––– °C/W

jk ––– 40

0.29

www.irf.com 1

A

5/21/08

IRFP4468PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

ΔV

(BR)DSS

R

DS(on)

V

GS(th)

I

DSS

I

GSS

R

G

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 310 ––– ––– S Q

g

Q

gs

Q

gd

Q

sync

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

eff. (ER)

C

oss

eff. (TR)

C

oss

Drain-to-Source Breakdown Voltage 100 ––– ––– V

/ΔT

Breakdown Voltage Temp. Coefficient ––– 0.09 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 2.0 2.6 Gate Threshold Voltage 2.0 ––– 4.0 V Drain-to-Source Leakage Current ––– ––– 20 μA

––– ––– 250 Gate-to-Source Forward Leakage ––– ––– 100 nA Gate-to-Source Reverse Leakage ––– ––– -100 Internal Gate Resistance ––– 0.8 ––– Ω

Total Gate Charge ––– 360 540 nC Gate-to-Source Charge ––– 81 ––– Gate-to-Drain ("Miller") Charge ––– 89 Total Gate Charge Sync. (Qg - Qgd)

––– 270 ––– Turn-On Delay Time ––– 52 ––– ns Rise Time ––– 230 ––– Turn-Off Delay Time ––– 160 ––– Fall Time ––– 260 ––– Input Capacitance ––– 19860 ––– pF Output Capacitance ––– 1360 ––– Reverse Transfer Capacitance ––– 540 –––

Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)

––– 1550 –––

––– 900 –––

h

VGS = 0V, ID = 250μA Reference to 25°C, I

= 10V, ID = 180A

V

mΩ

GS

= VGS, ID = 250μA

V

DS

= 100V, VGS = 0V

V

DS

= 80V, VGS = 0V, TJ = 125°C

V

DS

= 20V

V

GS

= -20V

V

GS

VDS = 50V, ID = 180A

= 180A

I

D

=50V

V

DS

= 10V

= 65V

= 0V = 50V

g

V

GS

I

= 180A, VDS =0V, VGS = 10V

D

V

DD

= 180A

I

D

= 2.7Ω

R

G

VGS = 10V V

GS

V

DS

ƒ = 100 kHz, See Fig. 5

= 0V, VDS = 0V to 80V i, See Fig. 11

V

GS

= 0V, VDS = 0V to 80V

V

GS

Conditions

= 5mA

D

g

Conditions

d

h

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

I

RRM

t

on

Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 195A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-1140)

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 25Ω, I above this value .

Continuous Source Current ––– –––

290

c

(Body Diode) Pulsed Source Current ––– ––– 1120 A

(Body Diode)

d

Diode Forward Voltage ––– ––– 1.3 V Reverse Recovery Time ––– 100 ns

––– 110 Reverse Recovery Charge ––– 370 nC

––– 420 Reverse Recovery Current ––– 6.9 ––– A Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

 I

≤ 180A, di/dt ≤ 600A/μs, V

SD

 Pulse width ≤ 400μs; duty cycle ≤ 2%.  C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

, starting TJ = 25°C, L = 0.045mH

Jmax

= 180A, VGS =10V. Part not recommended for use

AS

as C

 C

C

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 R

while V

oss

eff. (ER) is a fixed capacitance that gives the same energy as

oss

while V

oss

is measured at TJ approximately 90°C

θ

DS

is rising from 0 to 80% V

DS

A

MOSFET symbol

showing the integral reverse

p-n junction diode.

= 25°C, IS = 180A, VGS = 0V

T

J

TJ = 25°C VR = 85V,

= 125°C IF = 180A

T

J

TJ = 25°C

= 125°C

T

J

TJ = 25°C

≤ V

DD

(BR)DSS

is rising from 0 to 80% V

DSS

Conditions

di/dt = 100A/μs

, TJ ≤ 175°C.

.

DSS

.

D

G

S

g

2 www.irf.com

IRFP4468PbF

1000

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

TOP 15V

100

BOTTOM 4.0V

10

VGS

10V

8.0V

6.0V

5.5V

5.0V

4.5V

4.0V

≤

60μs PULSE WIDTH

Tj = 25°C

1

0.01 0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

)

Α

(

t n e

r

100

u C e

c

r u o S

o

t

n

10

i a

r D

,

D

I

1

TJ = 175°C

TJ = 25°C

V

= 25V

DS

≤

60μs PULSE WIDTH

2.0 3.0 4.0 5.0 6.0 7.0

VGS, Gate-to-Source Voltage (V)

1000

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

TOP 15V

BOTTOM 4.0V

100

VGS

10V

8.0V

6.0V

5.5V

5.0V

4.5V

4.0V

≤

60μs PULSE WIDTH

Tj = 175°C

10

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

2.5

e c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D

,

) n o

( S D

R

ID = 180A

V

= 10V

GS

2.0

) d e z

i

l a

1.5

m

r o

N

(

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

) F p

( e

c n a

t

i c a p a

C ,

C

35000

30000

25000

20000

15000

10000

5000

0

1 10 100

V

= 0V, f = 100 kHz

GS

C

= C

+ Cgd, C

gs

gd

+ C

ds

gd

C

iss

rss

oss

Ciss

Coss

Crss

VDS, Drain-to-Source Voltage (V)

SHORTED

Fig 4. Normalized On-Resistance vs. Temperature

16

ID= 180A

) V

( e

g

12

a

t

l o V

e c

r u o

8

S

o

t

e

t a

G ,

4

S G

V

0

0 50 100 150 200 250 300 350 400 450

VDS= 80V

VDS= 50V

VDS= 20V

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

www.irf.com 3

IRFP4468PbF

1000

) A

( t

100

n e

r

r u

C n

i a

r D e

s

r e v e

R ,

D S

I

TJ = 175°C

10

1

0.1

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TJ = 25°C

V

GS

= 0V

VSD, Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode

10000

) A

(

1000

t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

100

10

LIMITED BY PACKAGE

1

Tc = 25°C

OPERATION IN THIS AREA LIMITED BY RDS(on)

Tj = 175°C Single Pulse

0.1

0.1 1 10 100

VDS, Drain-toSource Voltage (V)

Fig 8. Maximum Safe Operating Area

100μsec

1msec

10msec

DC

Forward Voltage

300

LIMITED BY PACKAGE

250

) A

( t

200

n e

r

r u

C

150

n

i a

r D

,

100

D

I

50

0

25 50 75 100 125 150 175

TC , Case Temperature (°C)

Fig 9. Maximum Drain Current vs.

e g

120

a

t

l o V

n w

o d k a e

r B

e c

r u o S

o

t

n

i a

r D

,

V

ID = 5mA

110

100

S S D

) R B

(

90

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 10. Drain-to-Source Breakdown Voltage

Case Temperature

7.0

6.0

5.0

) J

μ

4.0

( y

g

r e

3.0

n E

2.0

1.0

0.0

0 20 40 60 80 100

V

Drain-to-Source Voltage (V)

DS,

3000

) J

m

( y

2500

g

r e n E

e

2000

h c n a

l a v

1500

A e

s

l u P

1000

e

l g n

i S

500

, S A

E

0

25 50 75 100 125 150 175

I

TOP

30A

41A

BOTTOM

Starting TJ, Junction Temperature (°C)

D

180A

Fig 11. Typical C

Stored Energy

OSS

Fig 12. Maximum Avalanche Energy Vs. DrainCurrent

4 www.irf.com

IRFP4468PbF

τ

1

)

C J h

t Z (

e s n o p s e

R l a

m

r e

0.001

h T

0.0001

1000

) A

( t n e

r

r u

C e

h c n a

l a v A

D = 0.50

0.1

0.20

0.10

R

2

3

R

2

τ

2

τ

2

Ri (°C/W)

R

3

τ

C

0.063359 0.000278

τ

3

τ

3

0.110878 0.005836

0.114838 0.053606

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.01

0.05

0.02

0.01

τ

J

τ

J

τ

1

Ci= τi/Ri

τ

1

Ci= τi/Ri

1

R

1

SINGLE PULSE ( THERMAL RESPONSE )

1E-006 1E-005 0.0001 0.001 0.01 0.1 1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100

10

Duty Cycle = Single Pulse

0.01

0.05

0.10

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

τι

(sec)

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤj = 25°C and

Tstart = 150°C.

1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

800

TOP Single Pulse

) J

m

600

( y

g

r e n E

e h

400

c n a

l a v A ,

R

200

A

E

0

25 50 75 100 125 150 175

BOTTOM 1% Duty Cycle ID = 180A

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T

2. Safe operation in Avalanche is allowed as long asT

. This is validated for every part type.

jmax

is not exceeded.

jmax

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P

= Average power dissipation per single avalanche pulse.

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ΔT = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14, 15). t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see Figures 13)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 15. Maximum Avalanche Energy vs. Temperature

www.irf.com 5

IRFP4468PbF

4.5

) V

4.0

( e

g a

t

l

3.5

o V

d

l o

3.0

h s e

r h

t

2.5

e

t a

G )

2.0

h

t

(

S G

1.5

V

1.0

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 1.0A

ID = 1.0mA

ID = 250μA

TJ , Temperature ( °C )

Fig 16. Threshold Voltage Vs. Temperature

40

32

)

24

A

(

M

R R

16

I

IF = 108A

8

0

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

VR = 85V

TJ = 125°C

TJ = 25°C

32

24

) A

(

-

16

M R R

I

8

0

100 200 300 400 500 600 700 800 900 1000

IF = 72A

VR = 85V

TJ = 125°C

TJ = 25°C

dif / dt - (A / μs)

Fig. 17 - Typical Recovery Current vs. dif/dt

1500

1000

) C

n

(

R

Q

500

0

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

IF = 72A

VR = 85V

TJ = 125°C

TJ = 25°C

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

2000

IF = 108A

VR = 85V

TJ = 125°C

1500

TJ = 25°C

) C

n

(

-

1000

R R

Q

500

0

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

Fig. 20 - Typical Stored Charge vs. dif/dt

6 www.irf.com

IRFP4468PbF

A





Reverse Recovery Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Current

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied Voltage

+

-

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

V

15V

V

DS

L

DRIVER

t

p

(BR)DSS

R

G

V

20V

GS

D.U.T

I

AS

0.01

t

p

Ω

+

V

DD

-

Fig 22a. Unclamped Inductive Test Circuit

R

V

GS

R

G

10V

V

GS

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

DS

D

D.U.T.

Fig 23a. Switching Time Test Circuit

Current Regulator

Same Type as D.U.T.

50KΩ

.2μF

12V

V

GS

3mA

.3μF

D.U.T.

+

V

DS

-

I

AS

Fig 22b. Unclamped Inductive Waveforms

V

DS

90%

+

V

DD

-

10% V

GS

t

d(on)tr

t

d(off)tf

Fig 23b. Switching Time Waveforms

Vds

Vgs(th)

Id

Vgs

I

G

Current Sampling Resistors

Fig 24a. Gate Charge Test Circuit

www.irf.com 7

I

D

Qgs1

Qgs2 Qgd Qgodr

Fig 24b. Gate Charge Waveform

IRFP4468PbF

TO-247AC Package Outline

Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information

EXAMPLE:

Note: "P" in ass embly line pos ition

TO-247AC packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

8 www.irf.com

THIS IS AN IR FPE 30 WI T H AS S E MB LY LOT CODE 5657

AS S EMBLE D ON WW 35, 2001 IN THE AS SEMBLY LINE "H"

in dicates "L ead-F ree"

INTER NATIONAL

RECTIF IER

LOGO

AS S E MB L Y LOT CODE

IRFP E30

135H

56 57

PAR T NUMBER

DATE CODE YEAR 1 = 2001 WEEK 35 LINE H

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 05/08