Datasheet IRFP4004PbF Datasheet

Applications

)

l High Efficiency Synchronous Rectification in

SMPS

l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits

Benefits

l Improved Gate, Avalanche and Dynamic

dv/dt Ruggedness

l Fully Characterized Capacitance and

Avalanche SOA

l Enhanced body diode dV/dt and dI/dt

Capability

PD - 97323

IRFP4004PbF

HEXFET® Power MOSFET

D

V

DSS

DS(on

typ.

R
max. 1.70m

G

I

D (Silicon Limited)

S

I

D (Package Limited)

D

S

D

G

40V

1.35m

350A

195A

Ω
Ω

c

TO-247AC

GDS

Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C

@ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

I

D

@ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited)

I

D

I

DM

P

@TC = 25°C

D

V

GS

dv/dt
T

J

T

STG

Continuous Drain Current, VGS @ 10V (Silicon Limited)

Pulsed Drain Current

Maximum Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Peak Diode Recovery

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Mounting torque, 6-32 or M3 screw

d

f

Max.

c

350

c

250

195

1390

380

2.5

± 20

2.0

-55 to + 175

300

10lbxin (1.1Nxm)

Avalanche Characteristics

g

e

290

See Fig. 14, 15, 22a, 22b

E

AS (Thermally limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

d

A

W

W/°C

V

V/ns

°C

mJ

A

mJ

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

Junction-to-Case

Case-to-Sink, Flat Greased Surface

Junction-to-Ambient

k

jk

–––

0.24 ––– °C/W
––– 40

0.40

www.irf.com 1

06/05/08

IRFP4004PbF

/

i

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

∆V

(BR)DSS

R

DS(on)

V

GS(th)

I

DSS

I

GSS

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 290 ––– ––– S
Q

g

Q

gs

Q

gd

Q

sync

R

G(int)

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

eff. (ER)

C

oss

eff. (TR)

C

oss

Drain-to-Source Breakdown Voltage 40 ––– ––– V

∆T

Breakdown Voltage Temp. Coefficient ––– 0.035 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 1.35 1.70

Gate Threshold Voltage 2.0 ––– 4.0 V

Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250

Gate-to-Source Forward Leakage ––– ––– 200 nA

Gate-to-Source Reverse Leakage ––– ––– -200

Total Gate Charge ––– 220 330 nC

Gate-to-Source Charge ––– 59 –––

Gate-to-Drain ("Miller") Charge ––– 75 –––
Total Gate Charge Sync. (Qg - Qgd)

Internal Gate Resistance

––– 145 –––

–––

6.8 –––

Turn-On Delay Time ––– 59 ––– ns

Rise Time ––– 370 –––

Turn-Off Delay Time ––– 160 –––

Fall Time ––– 190 –––

Input Capacitance ––– 8920 ––– pF

Output Capacitance ––– 2360 –––

Reverse Transfer Capacitance ––– 930 –––

Effective Output Capacitance (Energy Related)

Effective Output Capacitance (Time Related)

––– 2860 –––

––– 3110 –––

h

mΩ

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, I

V

= 10V, ID = 195A

GS

V

= VGS, ID = 250µA

DS

V

= 40V, VGS = 0V

DS

V

= 40V, VGS = 0V, TJ = 125°C

DS

V

= 20V

GS

V

= -20V

GS

Conditions

VDS = 10V, ID = 195A

I

= 195A

D

= 20V

V

DS

g

= 10V

V

GS

= 195A, VDS =0V, VGS = 10V

I

D

Ω

= 20V

V

DD

= 195A

I

D

R

= 2.7Ω

G

VGS = 10V

V

GS

V

DS

ƒ = 1.0MHz

V

GS

V

GS

g

= 0V

= 25V

= 0V, VDS = 0V to 32V

= 0V, VDS = 0V to 32V

= 5mA

D

g

d

i

h

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

I

RRM

t

on

Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. Refer to App Notes (AN-1140).

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 25Ω, I
above this value.

Continuous Source Current ––– –––

350

c

(Body Diode)
Pulsed Source Current ––– ––– 1390

(Body Diode)

di

Diode Forward Voltage ––– ––– 1.3 V

Reverse Recovery Time ––– 83 130 ns

––– 78 120

Reverse Recovery Charge ––– 190 290 nC

––– 210 320

Reverse Recovery Current ––– 4.0 ––– A

Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

 I

≤ 195A, di/dt ≤ 690A/µs, V

SD

 Pulse width ≤ 400µs; duty cycle ≤ 2%.
 C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

, starting TJ = 25°C, L = 0.015mH

Jmax

= 195A, VGS =10V. Part not recommended for use

AS

as C

 C

C

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 R

while V

oss

eff. (ER) is a fixed capacitance that gives the same energy as

oss

while V

oss

is measured at TJ approximately 90°C.

θ

is rising from 0 to 80% V

DS

is rising from 0 to 80% V

DS

Conditions

MOSFET symbol

A

showing the
integral reverse

p-n junction diode.
T

= 25°C, IS = 195A, VGS = 0V

J

T

= 25°C VR = 20V,

J

T

= 125°C IF = 195A

J

T

= 25°C

J

T

= 125°C

J

T

= 25°C

J

DD

≤ V

(BR)DSS

DSS

, TJ ≤ 175°C.

.

DSS

.

G

g

di/dt = 100A/µs

D

S

g

2 www.irf.com

IRFP4004PbF

1000

4.5V

VGS

10V

8.0V

7.0V

6.0V

5.5V

5.0V

60µs PULSE WIDTH

≤

TOP 15V

)
A

(
t
n
e

r

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

D

I

BOTTOM 4.5V

100

Tj = 25°C

10

0.1 1 10

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

)
A

(
t

n
e

r

100

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

D

I

10

TJ = 175°C

TJ = 25°C

V

= 10V

DS

60µs PULSE WIDTH

≤

1.0
3 4 5 6 7 8

VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

1000

4.5V

VGS

10V

8.0V

7.0V

6.0V

5.5V

5.0V

60µs PULSE WIDTH

≤

)
A

(
t
n
e

r

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,
I

TOP 15V

BOTTOM 4.5V

100

D

Tj = 175°C

10

0.1 1 10

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

2.0

e
c
n
a

t
s

i
s
e

R
n
O
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

)
n
o

(
S
D

R

)
d
e
z

i

l
a

m

r
o

N

(

1.5

1.0

ID = 195A

V

= 10V

GS

0.5

-60 -40 -20 0 20 40 60 80 100 120 140160 180

TJ , Junction Temperature (°C)

Fig 4. Normalized On-Resistance vs. Temperature

100000

)
F

10000

p

(
e

c
n
a

t

i
c
a
p
a

C

1000

,
C

100

V

= 0V, f = 1 MHZ

GS

C

= C

C

C

iss

rss

oss

+ Cgd, C

gs

= C

gd

= C

+ C

ds

C

iss

C

oss

C

rss

SHORTED

ds

gd

1 10 100

VDS, Drain-to-Source Voltage (V)

12.0
ID= 195A

)

10.0

V

(
e

g
a

t

l

8.0

o
V

e
c

r
u

6.0

o
S

­o

t

­e

t

4.0

a
G

,

S
G

2.0

V

VDS= 32V

VDS= 24V

0.0
0 50 100 150 200 250

QG, Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

www.irf.com 3

IRFP4004PbF

1000

)
A

(

100

t
n
e

r

r
u

C
n

i
a

r

10

D
e

s

r
e
v
e

R
,

D
S

I

0.1

TJ = 175°C

TJ = 25°C

1

V

= 0V

GS

0.0 0.4 0.8 1.2 1.6 2.0

VSD, Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage

350

300

)

250

A

(
t
n
e

r

200

r
u

C
n

i

150

a

r
D
,

D

100

I

50

0

25 50 75 100 125 150 175

TC , Case Temperature (°C)

Limited By Package

10000

OPERATION IN THIS AREA

)
A

(
t

1000

n
e

r

r
u

C
e

c

r

100

u
o
S

­o

t

­n

i
a

r
D

10

,

D

I

Tc = 25°C
Tj = 175°C
Single Pulse

1

110100

LIMITED BY RDS(on)

100µsec

1msec

10msec

DC

VDS, Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

)
V

52

(
e

g
a

t

l
o
V

n
w

o
d
k
a
e

r
B

e
c

r
u
o
S

­o

t

­n

i
a

r
D

,

S
S
D

)
R
B

(

V

Id = 5.0mA

50

48

46

44

42

40

-60 -40 -20 0 20 40 60 80 100 120 140160 180

TJ , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Case Temperature

2.5

2.0

)

1.5

J
µ

(
y

g

r
e
n

1.0

E

0.5

0.0

-5 0 5 10 15 20 25 30 35 40

V

Drain-to-Source Voltage (V)

DS,

Fig 11. Typical C

Stored Energy

OSS

Fig 12. Maximum Avalanche Energy vs. DrainCurrent

Fig 10. Drain-to-Source Breakdown Voltage

1200

)
J

m

(

1000

y
g

r
e
n
E

800

e
h
c
n
a

l
a

600

v
A

e
s

l
u

400

P
e

l
g
n

i
S

200

,

S
A

E

0

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

TOP 36A

BOTTOM 195A

I

73A

D

4 www.irf.com

IRFP4004PbF

τ

1

W

/
C

°
)

C
J
h

t

Z
(

e
s
n
o
p
s
e

0.01

R
l
a

m

r
e
h
T

0.001

1000

0.1

D = 0.50

0.20

0.10

0.05

0.02

0.01

SINGLE PULSE
( THERMAL RESPONSE )

τ

J

τ

J

τ

1

Ci= τi/Ri

R

R

R

R

1

2

R

1

τ

τ

1

2

τ

3

R

R

2

3

τ

3

τ

2

3

Ri (°C/W) τi (sec)

4

R

4

0.0123 0.000011

τ

C

τ

0.0585 0.000055

4

τ

4

0.1693 0.000917

0.1601 0.008784

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche

)
A

(

100

t
n
e

r

r
u

C
e

h
c
n
a

l

10

a
v

A

0.01

0.05

0.10

pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τj = 25°C and
Tstart = 150°C.

1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

300

TOP Single Pulse

250

)
J

m

(
y

200

g

r
e
n
E

e

150

h
c
n
a

l
a
v

100

A
,

R
A

E

50

BOTTOM 1.0% Duty Cycle
ID = 195A

0

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T

2. Safe operation in Avalanche is allowed as long asT

. This is validated for every part type.

jmax

is not exceeded.

jmax

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P

= Average power dissipation per single avalanche pulse.

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).

6. I

= Allowable avalanche current.

av

7. ∆T = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14, 15).
t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t
Z

(D, tav) = Transient thermal resistance, see Figures 13)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 15. Maximum Avalanche Energy vs. Temperature

www.irf.com 5

IRFP4004PbF

5.0

)

4.5

V

(
e

g

4.0

a

t

l
o
V

3.5

d

l
o
h
s
e

3.0

r
h

t
e

t
a

G
,

)
h

t

(
S
G

V

ID = 250µA

ID = 1.0mA

2.5
ID = 1.0A

2.0

1.5

1.0

-75 -50 -25 0 25 50 75 100 125 150 175 200

TJ , Temperature ( °C )

Fig 16. Threshold Voltage vs. Temperature

14

IF = 117A

VR = 34V

12

TJ = 25°C

TJ = 125°C

10

)
A

(

8

R
R

I

6

12

IF = 78A

VR = 34V

10

TJ = 25°C

TJ = 125°C

8

)
A

(

R
R

I

6

4

2

0 200 400 600 800 1000

diF /dt (A/µs)

Fig. 17 - Typical Recovery Current vs. dif/dt

350

IF = 78A

VR = 34V

300

TJ = 25°C

TJ = 125°C

250

)
A

(

200

R
R

Q

150

4

2

0 100 200 300 400 500 600

diF /dt (A/µs)

400

350

300

)
A

(

250

R
R

Q

200

150

100

100

50

0 200 400 600 800 1000

diF /dt (A/µs)

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

IF = 117A

VR = 34V

TJ = 25°C

TJ = 125°C

0 100 200 300 400 500 600

diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

6 www.irf.com

IRFP4004PbF

A

+

-





Reverse
Recovery
Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Current

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance
Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied
Voltage

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

V

15V

V

DS

L

DRIVER

t

p

(BR)DSS

R

V

20V

G

GS

D.U.T

I

AS

0.01

t

p

Ω

+

V

DD

-

Fig 21a. Unclamped Inductive Test Circuit

L

V

DS

D

+

-

V

DD

D.U.T

V

GS

Pulse Width < 1µs

Duty Factor < 0.1%

Fig 22a. Switching Time Test Circuit

L

0

DUT

1K

VCC

I

AS

Fig 21b. Unclamped Inductive Waveforms

V

DS

90%

10%

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig 22b. Switching Time Waveforms

Vds

Vgs(th)

Id

Vgs

Qgs1

Qgs2 Qgd Qgodr

Fig 23a. Gate Charge Test Circuit

www.irf.com 7

Fig 23b. Gate Charge Waveform

IRFP4004PbF

TO-247AC Package Outline

Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information

(;$03/(

1RWH3LQDVVHPEO\OLQHSRVLWLRQ

TO-247AC package is not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

8 www.irf.com

7+,6,6$1,5)3(
:,7+$66(0%/<

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LQGLFDWHV/HDG)UHH

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

,17(51$7,21$/

5(&7,),(5

/2*2

$66(0%/<
/27&2'(

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

Visit us at www.irf.com for sales contact information. 06/08

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TAC Fax: [phone]