This N-Channel enhancementmode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdownavalanchemodeof operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17434.
Ordering Information
PART NUMBERPACKAGEBRAND
IRFP350TO-247IRFP350
NOTE: When ordering, include the entire part number.
File Number
Features
• 16A, 400V
•r
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
= 0.300Ω
Components to PC Boards”
Symbol
D
G
2319.4
Packaging
DRAIN
(FLANGE)
S
JEDEC STYLE TO-247
TOP VIEW
SOURCE
DRAIN
GATE
4-335
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
700mJ
-55 to 150
300
260
o
C
o
C
o
C
NOTE:
1. TJ= 25oC to 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate to Threshold VoltageV
GS(TH)VGS
Zero-Gate Voltage Drain CurrentI
On-State Drain Current (Note 2)I
D(ON)
Gate to Source Leakage CurrentI
DraintoSource OnResistance(Note 2)r
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
0.75
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.60
39
VGS = 10V
VGS = 20V
52
0.45
0.30
, DRAIN TO SOURCE
ON RESISTANCE
0.15
DS(ON)
r
0
065
1326
ID,DRAIN CURRENT (A)
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
= 8.9A, VGS = 10V
I
D
2.0
1.5
1.0
0.5
ON RESISTANCE VOLTAGE
NORMALIZED DRAIN TO SOURCE
0
060120160
-20-4020 40100140
T
, JUNCTION TEMPERATURE (oC)
J
80-60
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4-338
FIGURE 9. NORMALIZED DRAIN TOSOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Page 5
IRFP350
Typical Performance Curves
1.25
ID = 250µA
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-2020100160
0-404080120 140
T
, JUNCTION TEMPERATURE (oC)
J
Unless Otherwise Specified (Continued)
60-60
FIGURE 10. NORMALIZED DRAINTOSOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
25
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
= 2 x V
V
DS
20
15
GS
TJ = 25oC
5000
4000
RSS
C
C
OSS
3000
2000
C, CAPACITANCE (pF)
1000
0
121025
C
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
ISS
VGS = 0V, f = 1MHz
= CGS + C
C
C
C
ISS
RSS
OSS
= C
≈ C
GD
DS
GD
+ C
GS
10
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
2
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
10
2
10
, TRANSCONDUCTANCE (S)
5
fs
g
0
TJ = 150oC
TJ = 150oC
5101520025
ID, DRAIN CURRENT (A)
1
, SOURCE TO DRAIN CURRENT (A)
SD
I
0.1
00.40.81.21.62.0
VSD, SOURCE TO DRAIN VOLTAGE (V)
TJ = 25oC
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE FORWARD VOLTAGE
20
ID = 16A
16
VDS = 80V
12
8
4
GATE TO SOURCE VOLTAGE (V)
GS,
V
0
3060901200150
VDS = 200V
Qg, GATE CHARGE (nC)
V
DS
= 320V
4-339
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Page 6
IRFP350
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
+
V
DD
-
DUT
0V
P
I
AS
0.01Ω
0
t
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
P
I
AS
t
AV
V
DS
V
DD
R
G
V
GS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
CURRENT
REGULATOR
12V
BATTERY
0.2µF
50kΩ
0.3µF
t
ON
t
d(ON)
t
R
L
+
V
DD
-
V
DS
0
r
90%
10%
DUT
V
GS
10%
0
50%
PULSE WIDTH
t
d(OFF)
90%
t
OFF
50%
t
f
10%
90%
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED
SUPPLY)
SAME TYPE
AS DUT
V
DD
Q
g(TOT)
Q
gd
Q
gs
V
GS
G
I
0
G(REF)
IG CURRENT
SAMPLING
RESISTORRESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT
4-340
D
S
CURRENT
I
D
SAMPLING
DUT
V
DS
0
V
DS
I
G(REF)
0
FIGURE 20. GATE CHARGE WAVEFORMS
Page 7
IRFP350
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
4-341
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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