Datasheet IRFP3306PBF Datasheet (International Rectifier)

)

PD - 97128

IRFP3306PbF

HEXFET® Power MOSFET

Applications

l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

G

D

V

DSS

R

DS(on

max.
I

D

(Silicon Limited)

I

D

S

(Package Limited)

D

typ.

SOA

l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free

S

D

G

TO-247AC

GDS

Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

@ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

I

D

@ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited)

I

D

I

DM

@TC = 25°C

P

D

V

GS

dv/dt
T

J

T

STG

Pulsed Drain Current

Maximum Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Peak Diode Recovery

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Mounting torque, 6-32 or M3 screw

d

f

Max.

c

160

110

120

620

220

1.5

± 20

14

-55 to + 175

300

10lbxin (1.1Nxm)

60V

3.3m

4.2m

160A

120A

W/°C

V/ns

:
:

c

A

W

V

°C

Avalanche Characteristics

g

e

184

See Fig. 14, 15, 22a, 22b,

mJ

mJ

E

AS (Thermally limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

d

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

Junction-to-Case

Case-to-Sink, Flat Greased Surface

Junction-to-Ambient

k –––

0.24 ––– °C/W

jk ––– 40

0.67

www.irf.com 1

A

3/3/08

IRFP3306PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

ΔV

(BR)DSS

R

DS(on)

V

GS(th)

I

DSS

I

GSS

R

G

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 230 ––– ––– S

Q

g

Q

gs

Q

gd

Q

sync

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

eff. (ER)

C

oss

eff. (TR)

C

oss

Drain-to-Source Breakdown Voltage 60 ––– ––– V

/ΔT

Breakdown Voltage Temp. Coefficient ––– 0.07 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 3.3 4.2

Gate Threshold Voltage 2.0 ––– 4.0 V

Drain-to-Source Leakage Current ––– ––– 20 μA

––– ––– 250

Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

Internal Gate Resistance ––– 0.7 ––– Ω

Total Gate Charge ––– 85 120 nC

Gate-to-Source Charge ––– 20 –––

Gate-to-Drain ("Miller") Charge ––– 26

Total Gate Charge Sync. (Qg - Qgd)

––– 59 –––

Turn-On Delay Time ––– 15 ––– ns

Rise Time ––– 76 –––

Turn-Off Delay Time ––– 40 –––

Fall Time ––– 77 –––

Input Capacitance ––– 4520 ––– pF

Output Capacitance ––– 500 –––

Reverse Transfer Capacitance ––– 250 –––

Effective Output Capacitance (Energy Related)

Effective Output Capacitance (Time Related)h

––– 720 –––

––– 880 –––

VGS = 0V, ID = 250μA

Reference to 25°C, I

= 10V, ID = 75A g

V

mΩ

GS

= VGS, ID = 150μA

V

DS

= 60V, VGS = 0V

V

DS

= 48V, VGS = 0V, TJ = 125°C

V

DS

VGS = 20V

= -20V

V

GS

VDS = 50V, ID = 75A

= 75A

I

D

V

=30V

DS

V

= 10V g

GS

I

= 75A, VDS =0V, VGS = 10V

D

V

= 30V

DD

ID = 75A

= 2.7Ω

R

G

VGS = 10V g

= 0V

V

GS

= 50V

V

DS

ƒ = 1.0MHz, See Fig. 5

= 0V, VDS = 0V to 48V i, See Fig. 11

V

GS

= 0V, VDS = 0V to 48V h

V

GS

Conditions

= 5mAd

D

Conditions

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

I

RRM

t

on

Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 25Ω, I
above this value .

Continuous Source Current ––– –––

160c

(Body Diode)
Pulsed Source Current ––– ––– 620 A

(Body Diode)d
Diode Forward Voltage ––– ––– 1.3 V

Reverse Recovery Time ––– 31 ns

––– 35

Reverse Recovery Charge ––– 34 nC

––– 45

Reverse Recovery Current ––– 1.9 ––– A

Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

 I

≤ 75A, di/dt ≤ 1400A/μs, V

SD

 Pulse width ≤ 400μs; duty cycle ≤ 2%.
 C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

, starting TJ = 25°C, L = 0.04mH

Jmax

= 96A, VGS =10V. Part not recommended for use

AS

as C

 C

C

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 R

while V

oss

eff. (ER) is a fixed capacitance that gives the same energy as

oss

while V

oss

is measured at TJ approximately 90°C

θ

DS

is rising from 0 to 80% V

DS

MOSFET symbol

A

showing the
integral reverse

p-n junction diode.

= 25°C, IS = 75A, VGS = 0V g

T

J

TJ = 25°C VR = 51V,

= 125°C IF = 75A

T

J

TJ = 25°C

= 125°C

T

J

TJ = 25°C

≤ V

DD

(BR)DSS

is rising from 0 to 80% V

DSS

Conditions

di/dt = 100A/μs g

, TJ ≤ 175°C.

.

DSS

.

D

G

S

2 www.irf.com

IRFP3306PbF

1000

)
A

(
t
n
e

r

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

D

I

TOP 15V

BOTTOM 4.5V

100

VGS

10V

8.0V

6.0V

5.5V

5.0V

4.8V

4.5V

≤

60μs PULSE WIDTH

Tj = 25°C

10

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

)

Α

(

t
n

100

e

r

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

D

I

TJ = 175°C

10

TJ = 25°C

1

V

= 25V

DS

≤

0.1

2.0 3.0 4.0 5.0 6.0 7.0 8.0

60μs PULSE WIDTH

VGS, Gate-to-Source Voltage (V)

1000

)
A

(
t
n
e

r

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

D

I

TOP 15V

BOTTOM 4.5V

100

VGS

10V

8.0V

6.0V

5.5V

5.0V

4.8V

4.5V

≤

60μs PULSE WIDTH

Tj = 175°C

10

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

2.5

e
c
n
a

t
s

i
s
e

R
n
O
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

)
n
o

(
S
D

R

ID = 75A

V

= 10V

GS

2.0

)
d
e
z

i

l
a

1.5

m

r
o

N

(

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

8000

6000

)
F
p

(
e

c
n
a

t

i

4000

c
a
p
a

C
,

C

2000

V

= 0V, f = 1 MHZ

GS

C

= C

iss

gs

C

= C

rss

oss

= C

gd

ds

C

Ciss

Coss

+ Cgd, C

+ C

gd

ds

SHORTED

Fig 4. Normalized On-Resistance vs. Temperature

20

ID= 75A

)
V

(

16

e
g
a

t

l
o
V

e

12

c

r
u
o
S

­o

t

8

­e

t
a

G
,

S

4

G

V

VDS= 48V

VDS= 30V
VDS= 12V

Crss

0

1 10 100

VDS, Drain-to-Source Voltage (V)

0

0 20 40 60 80 100 120 140

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

www.irf.com 3

IRFP3306PbF

1000

)
A

(
t

100

n
e

r

r
u

C
n

i
a

r
D
e

s

r
e
v
e

R
,

D
S

I

TJ = 175°C

10

1

0.1

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VSD, Source-to-Drain Voltage (V)

TJ = 25°C

V

GS

= 0V

Fig 7. Typical Source-Drain Diode

10000

)
A

(

1000

t
n
e

r

r
u

C

100

e
c

r
u
o
S

­o

t

10

­n

i
a

r
D

,

1

D

I

Tc = 25°C
Tj = 175°C
Single Pulse

0.1

0.1 1 10 100

OPERATION IN THIS AREA
LIMITED BY RDS(on)

1msec

10msec

VDS, Drain-toSource Voltage (V)

Fig 8. Maximum Safe Operating Area

100μsec

DC

Forward Voltage

180

160

140

)
A

(

120

t
n
e

r

r

100

u
C
n

i

80

a

r
D

60

,

D

I

40

20

0

25 50 75 100 125 150 175

TC , Case Temperature (°C)

Limited By Package

Fig 9. Maximum Drain Current vs.

e
g

80

a

t

l
o
V

n
w

o
d
k
a
e

r
B

e
c

r
u
o
S

­o

t

­n

i
a

r
D

,

V

ID = 5mA

70

60

S
S
D

)
R
B

(

50

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 10. Drain-to-Source Breakdown Voltage

Case Temperature

1.5

1.0

)
J

μ

(
y

g

r
e
n
E

0.5

0.0

0 10 20 30 40 50 60

V

Drain-to-Source Voltage (V)

DS,

800

)
J

m

(
y

g

r
e

600

n
E

e
h
c
n
a

l
a
v

400

A
e

s

l
u
P

e

l
g

200

n

i
S

,
S
A

E

0

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

I

TOP

18A

BOTTOM

D

13A

96A

Fig 11. Typical C

Stored Energy

OSS

Fig 12. Maximum Avalanche Energy Vs. DrainCurrent

4 www.irf.com

IRFP3306PbF

1

D = 0.50

)

0.1

C
J
h

t
Z
(

e
s
n
o

0.01

p
s
e

R
l
a

m

r
e

0.001

h
T

0.0001

1E-006 1E-005 0.0001 0.001 0.01 0.1

100

)
A

(
t
n
e

r

r
u

C

10

e
h
c
n
a

l
a
v
A

0.20

0.10

0.05

0.02

R

R

1

2

R

0.01

SINGLE PULSE
( THERMAL RESPONSE )

τ

J

τ

J

τ

1

τ

Ci= τi/Ri

1

1

Notes:

R

2

Ri (°C/W)

τ

C

τ

2

0.249761 0.00028

τ

2

0.400239 0.005548

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Duty Cycle = Single Pulse

0.01

0.05

0.10

Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤj = 25°C and

Tstart = 150°C.

Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

τι

(sec)

1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

200

TOP Single Pulse

)
J

160

m

(
y

g

r
e
n

120

E
e

h
c
n
a

l

80

a
v

A
,

R
A

40

E

0

25 50 75 100 125 150 175

BOTTOM 1% Duty Cycle
ID = 96A

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T

2. Safe operation in Avalanche is allowed as long asT

. This is validated for every part type.

jmax

is not exceeded.

jmax

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P

= Average power dissipation per single avalanche pulse.

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).

6. I

= Allowable avalanche current.

av

7. ΔT = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14, 15).
t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t
Z

(D, tav) = Transient thermal resistance, see Figures 13)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 15. Maximum Avalanche Energy vs. Temperature

www.irf.com 5

IRFP3306PbF

4.5

)
V

4.0

(
e

g
a

t

l

3.5

o
V

d

l
o

3.0

h
s
e

r
h

t

2.5

e

t
a

G
)

2.0

h

t

(

S
G

1.5

V

1.0

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 1.0A

ID = 1.0mA

ID = 250μA

ID = 150μA

TJ , Temperature ( °C )

Fig 16. Threshold Voltage Vs. Temperature

16

12

)
A

(

-

8

M
R
R

I

4

0

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

IF = 45A

VR = 51V

TJ = 125°C

TJ = 25°C

16

12

)
A

(

-

8

M
R
R

I

4

0

100 200 300 400 500 600 700 800 900 1000

IF = 30A

VR = 51V

TJ = 125°C

TJ = 25°C

dif / dt - (A / μs)

Fig. 17 - Typical Recovery Current vs. dif/dt

350

300

250

)
C

200

n

(

­R

150

R

Q

100

50

0

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

IF = 30A

VR = 51V

TJ = 125°C

TJ = 25°C

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

350

300

250

)
C

200

n

(

­R

150

R

Q

100

50

0

100 200 300 400 500 600 700 800 900 1000

IF = 45A

VR = 51V

TJ = 125°C

TJ = 25°C

dif / dt - (A / μs)

Fig. 20 - Typical Stored Charge vs. dif/dt

6 www.irf.com

IRFP3306PbF

A





Reverse
Recovery
Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Current

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance
Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied
Voltage

+

-

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

V

15V

V

DS

L

DRIVER

t

p

(BR)DSS

R

G

V

20V

GS

D.U.T

I

AS

0.01

t

p

Ω

+

V

DD

-

Fig 22a. Unclamped Inductive Test Circuit

L

V

DS

D

+

-

V

DD

D.U.T

V

GS

Pulse Width < 1μs

Duty Factor < 0.1%

Fig 23a. Switching Time Test Circuit

Current Regulator

Same Type as D.U.T.

50KΩ

.2μF

12V

V

GS

3mA

.3μF

D.U.T.

+

V

DS

-

I

AS

Fig 22b. Unclamped Inductive Waveforms

V

DS

90%

10%

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig 23b. Switching Time Waveforms

Vds

Vgs(th)

Id

Vgs

I

Current Sampling Resistors

Fig 24a. Gate Charge Test Circuit

www.irf.com 7

I

G

D

Qgs1

Qgs2 Qgd Qgodr

Fig 24b. Gate Charge Waveform

IRFP3306PbF

TO-247AC Package Outline

Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information

EXAMPLE:

Note: "P" in ass embly line pos ition

TO-247AC packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

8 www.irf.com

THIS IS AN IRFPE 30
WI T H AS S E MB LY
LOT CODE 5657

AS S EMBLE D ON WW 35, 2001
IN THE AS SEMBLY LINE "H"

in dicates "L ead-F ree"

INTER NATIONAL

RECTIF IER

LOGO

AS S E MB L Y
LOT CODE

IRFP E30

135H

56 57

PAR T NUMBER

DATE CODE
YEAR 1 = 2001
WEEK 35
LINE H

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

TAC Fax: [phone]

Visit us at www.irf.com for sales contact information. 03/08