Datasheet irfp150v Datasheet

PD - 94459A

IRFP150V

HEXFET® Power MOSFET

l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 175°C Operating Temperature l Fast Switching l Fully Avalanche Rated

G

D

V

R

DS(on)

DSS

= 100V

= 24mΩ

ID = 47A

S

Description

Advanced HEXFET® Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.

The TO-247 package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220 devices. The TO-247 is similar but superior to the earlier TO-218 packcage because of its isolated

TO-247AC

mounting hole.

Absolute Maximum Ratings

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 46 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 32 A I

DM

PD @TC = 25°C Power Dissipation 140 W

V

GS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt  5.8 V/ns T

J

T

STG

Pulsed Drain Current  230

Linear Derating Factor 0.91 W/°C Gate-to-Source Voltage ± 20 V Avalanche Current 28 A Repetitive Avalanche Energy 20 mJ

Operating Junction and -55 to + 175 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)

°C

Thermal Resistance

Parameter Typ. Max. Units

R

θJC

R

θCS

R

θJA

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Junction-to-Case ––– 1.1 Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W Junction-to-Ambient ––– 40

02/03/03

IRFP150V

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions

V

(BR)DSS

∆V

(BR)DSS

R

DS(on)

V

GS(th)

g

fs

I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

C

iss

C

oss

C

rss

E

AS

Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA

/∆T

Breakdown Voltage Temp. Coefficient ––– 0.13 ––– V/°C Reference to 25°C, ID = 1mA

J

Static Drain-to-Source On-Resistance ––– ––– 24 mΩ VGS = 10V, ID =28A  Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA Forward Transconductance 32 ––– ––– S VDS = 25V, ID = 28A

Drain-to-Source Leakage Current

––– ––– 25

––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V Gate-to-Source Reverse Leakage ––– ––– -100

VDS = 100V, VGS = 0V

µA

nA

VGS = -20V Total Gate Charge ––– ––– 130 ID = 28A Gate-to-Source Charge ––– ––– 26 nC VDS = 80V Gate-to-Drain ("Miller") Charge ––– ––– 43 VGS = 10V, See Fig. 6 and 13 Turn-On Delay Time ––– 12 ––– VDD = 50V Rise Time ––– 58 ––– ID = 28A Turn-Off Delay Time ––– 45 ––– RG = 2.5Ω

ns

Fall Time ––– 47 ––– VGS = 10V, See Fig. 10 

4.5

Internal Drain Inductance

Internal Source Inductance ––– –––

––– –––

7.5

Between lead,

6mm (0.25in.)

nH

from package

and center of die contact Input Capacitance ––– 3130 ––– VGS = 0V Output Capacitance ––– 410 ––– VDS = 25V Reverse Transfer Capacitance ––– 72 ––– pF ƒ = 1.0MHz, See Fig. 5 Single Pulse Avalanche Energy ––– 1060280 mJ I

= 28A, L = 0.70mH

AS

D

G

S

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode)

––– –––

47

230

showing the

A

p-n junction diode.

G

Diode Forward Voltage ––– ––– 1.2 V TJ = 25°C, IS = 28A, VGS = 0V  Reverse Recovery Time ––– 140 220 ns TJ = 25°C, IF = 28A Reverse Recovery Charge ––– 670 1010 nC di/dt = 100A/µs



Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Starting T

I

AS

 I

SD

= 25°C, L = 0.70mH, RG = 25Ω,

J

= 28A, VGS=10V (See Figure 12). ≤ 28A, di/dt ≤ 380A/µs, V

DD

≤ V

(BR)DSS

,

 Pulse width ≤ 400µs; duty cycle ≤ 2%.  This is a typical value at device destruction and represents

operation outside rated limits.

 This is a calculated value limited to T

= 175°C .

J

TJ ≤ 175°C.

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D

S

IRFP150V

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

1000

TOP 16V

100

BOTTOM 3.5V

10

1

D

VGS

10V

7.0V

6.0V

5.0V

4.5V

4.0V

3.5V

20µs PULSE WIDTH Tj = 25°C

0.1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

1000.00

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

1000

TOP 16V

100

BOTTOM 3.5V

10

1

D

VGS

10V

7.0V

6.0V

5.0V

4.5V

4.0V

3.5V

20µs PULSE WIDTH Tj = 175°C

0.1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

3.0

57A

I =

D

)

Α

(

100.00

t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

TJ = 175°C

10.00

TJ = 25°C

1.00

V

= 15V

DS

0.10

3.0 4.0 5.0 6.0 7.0 8.0 9.0

20µs PULSE WIDTH

VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

2.5

2.0

1.5

(Normalized)

1.0

0.5

DS(on)

R , Drain-to-Source On Resistance

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

T , Junction Temperature ( C)

J

Fig 4. Normalized On-Resistance

V =

GS

°

10V

Vs. Temperature

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IRFP150V

100000

10000

) F p

( e c n a

t

i

1000

c a p a

C ,

C

100

10

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

iss

gs

C

= C

rss

gd

C

= C

ds

+ C

oss

Coss

+ Cgd, C

gd

Ciss

Crss

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000.00

) A

( t

100.00

n e

r

r u

C n

i a

r D e

s

r e v e

R ,

D S

I

10.00

1.00

0.10

TJ = 175°C

TJ = 25°C

0.0 0.5 1.0 1.5 2.0

VSD, Source-toDrain Voltage (V)

SHORTED

ds

V

= 0V

GS

12

D

I =

28A

10

7

5

2

GS

V , Gate-to-Source Voltage (V)

0

0 20 40 60 80 100

Q , Total Gate Charge (nC)

G

V = 80V

DS

V = 50V

DS

V = 20V

DS

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

) A

( t

100

n e

r

r u

C e

c

r

10

u o S

o

t

n

i a

r

1

D ,

D

Tc = 25°C

I

Tj = 175°C Single Pulse

0.1 1 10 100 1000

OPERATION IN THIS AREA LIMITED BY RDS(on)

V

, Drain-toSource Voltage (V)

DS

100µsec

1msec

10msec

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

4 www.irf.com

IRFP150V

+

-

50

40

30

20

D

I , Drain Current (A)

10

0

25 50 75 100 125 150 175

T , Case Temperature ( C)

C

°

Fig 9. Maximum Drain Current Vs.

Case Temperature

10

R

V

DS

V

GS

R

G

V

GS

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

D

D.U.T.

Fig 10a. Switching Time Test Circuit

V

DS

90%

10% V

GS

t

d(on)tr

t

d(off)tf

Fig 10b. Switching Time Waveforms

V

DD

thJC

1

D = 0.50

0.20

P

1 2

DM

t

1

t

2

0.10

0.1

0.05

Thermal Response (Z )

0.02

0.01

0.00001 0.0001 0.001 0.01 0.1 1

SINGLE PULSE

(THERMAL RESPONSE)

t , Rectangular Pulse Duration (sec)

1

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

J DM thJC C

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com 5

IRFP150V

A

15V

DRIVER

+

-

V

DD

R

20V

V

DS

G

GS

L

D.U.T

I

AS

Ω

0.01

t

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

I

AS

Fig 12b. Unclamped Inductive Waveforms

550

TOP

440

330

220

110

AS

E , Single Pulse Avalanche Energy (mJ)

0

25 50 75 100 125 150 175

Starting T , Junction Temperature ( C)

J

BOTTOM

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Current Regulator

Same Type as D.U.T.

I

D

11A

20A

28A

°

50KΩ

Q

G

V

GS

Q

GS

V

G

Q

GD

Charge

Fig 13a. Basic Gate Charge Waveform

12V

Fig 13b. Gate Charge Test Circuit

.2µF

.3µF

D.U.T.

V

GS

3mA

I

G

Current Sampling Resistors

I

D

6 www.irf.com

+

V

DS

-

IRFP150V

+

-

Peak Diode Recovery dv/dt Test Circuit

D.U.T*

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance Current Transformer

-

+



-



-

+



R

G

V

GS

• dv/dt controlled by R

• ISD controlled by Duty Factor "D"

G

• D.U.T. - Device Under Test

V

DD

* Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive

P.W.

Period

D =

P. W .

Period

VGS=10V

[ ] ***

D.U.T. ISDWaveform

Reverse Recovery Current

Re-Applied Voltage

D.U.T. VDSWaveform

Inductor Curent

*** V

= 5.0V for Logic Level and 3V Drive Devices

GS

Fig 14. For N-channel HEXFET

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

®

power MOSFETs

V

DD

[ ]

I

[ ]

SD

www.irf.com 7

IRFP150V

TO - 247 Package Outline

Dimensions are shown in millimeters (inches)

- D -

3X

20.30 (.800)

19.70 (.775)

14.80 (.583)

14.20 (.559)

2.40 (.094)

2.00 (.079) 2X

5.45 (.215)

2X

15.90 (.626)

15.30 (.602)

- B -

12

3

3X

3.40 (.133)

3.00 (.118)

- A -

5.50 (.217)

2X

- C -

4.30 (.170)

3.70 (.145)

1.40 (.056)

1.00 (.039)

0.25 (.010)

3.65 (.143)

3.55 (.140)

0.25 (.010)

5.50 (.217)

4.50 (.177)

M

MMB

CA

D

S

TO-247 package is not recommended for Surface Mount Application.

5.30 (.209)

4.70 (.185)

2.50 (.089)

1.50 (.059) 4

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-247-AC.

0.80 (.031)

0.40 (.016)

2.60 (.102)

2.20 (.087)

LEAD ASS IGNMENTS

1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.02/03

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