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PD - 9.1404A
TO-220 FULLPAK
PRELIMINARY
IRFI5210
HEXFET® Power MOSFET
l Advanced Process Technology
l Isolated Package
l High Voltage Isolation = 2.5KVRMS
l Sink to Lead Creepage Dist. = 4.8mm
l P-Channel
l Fully Avalanche Rated
G
D
V
R
DS(on)
= -100V
DSS
= 0.06Ω
ID = -23A
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab
and external heatsink. This isolation is equivalent to using
a 100 micron mica barrier with standard TO-220 product.
The Fullpak is mounted to a heatsink using a single clip or
by a single screw fixing.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -23
ID @ TC = 100°C Continuous Drain Current, VGS @ -10V -16 A
I
DM
PD @TC = 25°C Power Dissipation 63 W
V
GS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt -5.0 V/ns
T
J
T
STG
Pulsed Drain Current -140
Linear Derating Factor 0.42 W/°C
Gate-to-Source Voltage ± 20 V
Single Pulse Avalanche Energy 690 mJ
Avalanche Current -21 A
Repetitive Avalanche Energy 6.3 mJ
Operating Junction and -55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
Junction-to-Case ––– 2.4
Junction-to-Ambient ––– 65
S
°C/W
°C
3/16/98
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IRFI5210
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
C Drain to Sink Capacitance ––– 12 ––– ƒ = 1.0MHz
Drain-to-Source Breakdown Voltage -100 ––– ––– V VGS = 0V, ID = -250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– -0.11 ––– V/°C Reference to 25°C, ID = -1mA
J
Static Drain-to-Source On-Resistance ––– ––– 0.06 Ω VGS = 10V, ID = -12A
Gate Threshold Voltage -2.0 ––– -4.0 V VDS = VGS, ID = -250µA
Forward Transconductance 10 ––– ––– S VDS = -50V, ID = -21A
Drain-to-Source Leakage Current
––– ––– -25
––– ––– -250 VDS = -80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100
VDS = -100V, VGS = 0V
µA
nA
VGS = -20V
Total Gate Charge ––– ––– 180 ID = -21A
Gate-to-Source Charge ––– ––– 25 nC VDS = -80V
Gate-to-Drain ("Miller") Charge ––– ––– 97 VGS = -10V, See Fig. 6 and 13
Turn-On Delay Time ––– 17 ––– VDD = -50V
Rise Time ––– 86 ––– ID = -21A
Turn-Off Delay Time ––– 79 ––– RG = 2.5Ω
ns
Fall Time ––– 81 ––– RD = 2.4Ω, See Fig. 10
4.5
Internal Drain Inductance
Internal Source Inductance ––– –––
––– –––
7.5
Between lead,
6mm (0.25in.)
nH
from package
and center of die contact
Input Capacitance ––– 2700 ––– VGS = 0V
Output Capacitance ––– 790 ––– VDS = -25V
Reverse Transfer Capacitance ––– 450 ––– ƒ = 1.0MHz, See Fig. 5
pF
D
G
S
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
V
DD
RG = 25Ω, I
I
SD
TJ ≤ 175°C
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
Diode Forward Voltage ––– ––– -1.3 V TJ = 25°C, IS = -12A, VGS = 0V
Reverse Recovery Time ––– 170 260 ns TJ = 25°C, IF = -21A
Reverse RecoveryCharge ––– 1.2 1.8 µC di/dt = -100A/µs
Pulse width ≤ 300µs; duty cycle ≤ 2%.
= -25V, starting TJ = 25°C, L = 3.1mH
= -21A. (See Figure 12)
AS
≤ -21A, di/dt ≤ -480A/µs, V
DD
≤ V
(BR)DSS
t=60s, ƒ=60Hz
Uses IRF5210 data and test conditions
,
-23
-140
showing the
A
p-n junction diode.
D
G
S
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IRFI5210
A
A
A
)
A
1000
VGS
TOP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
100
10
D
-I , D ra in- to- S o ur ce Curre n t (A )
-4.5 V
40µs PU LS E WIDTH
T = 25°C
1
0.1 1 10 100
-V , D ra in-to-S o u rce V o ltage (V)
DS
c
Fig 1. Typical Output Characteristics
1000
1000
VGS
TOP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
100
10
D
-I , D ra in- to- S ou rc e C u rre n t (A )
-4.5 V
40µs PU LS E WIDTH
T = 175°C
1
0.1 1 10 100
-V , D ra in-to-S o u rce V o ltage (V )
DS
C
Fig 2. Typical Output Characteristics
3.0
I = -35A
D
100
10
D
-I , Dra in - to - S our c e Cur rent ( A )
1
45678910
-V , G a te - to -S o urce V o ltage (V
GS
T = 25°C
J
T = 175°C
J
V = -50V
DS
40µs PULSE W IDTH
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(N o rmaliz ed )
1.0
0.5
DS(on)
R , D ra in -to -S o u rc e On Res ista n c e
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Tem pe rature (°C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V = -10 V
GS
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IRFI5210
A
A
A
A
6000
5000
4000
3000
2000
C, Capacitance (pF)
1000
0
1 10 100
V = 0V, f = 1MHz
GS
C = C + C , C SHORTED
iss g s gd d s
C = C
rss g d
C = C + C
oss d s g d
C
iss
C
oss
C
rss
-V , Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
20
I = -21 A
16
12
GS
D
8
4
V = -80 V
DS
V = -50 V
DS
V = -20 V
DS
-V , Gate- to- S ou rc e V o lta ge (V)
FOR TEST CIRCUIT
0
0 40 80 120 160 200
Q , To ta l Gate C harge (n C)
G
SEE FIGURE 13
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
O P E R A T IO N IN TH IS A R EA L IM IT E D
BY R
DS(on)
100
T = 175°C
J
T = 25°C
J
10
SD
-I , R e ve rs e D ra in C u rre nt (A )
1
0.4 0.8 1.2 1.6 2.0 2.4
-V , Source-to-Drain Voltage (V)
SD
V = 0V
Fig 7. Typical Source-Drain Diode
Forward Voltage
GS
100
10
D
-I , Drain C urrent (A)
T = 2 5° C
C
T = 175°C
J
Single P ulse
1
1 10 100 1000
-V , D ra in-to-S o u rce V o ltage (V )
DS
10µs
100µs
1ms
10ms
Fig 8. Maximum Safe Operating Area
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IRFI5210
R
D.U.T.
D
-
+
V
DD
V
25
R
20
G
DS
V
GS
15
10
D
-I , Drain Current (A)
5
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
10%
90%
V
DS
-10V
t
d(on)tr
t
d(off)tf
Case Temperature
10
thJC
D = 0.50
1
0.20
0.10
P
1 2
DM
t
1
t
2
0.05
0.1
0.02
Thermal Response (Z )
0.01
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.00001 0.0001 0.001 0.01 0.1 1 10 100
t , Rectangular Pulse Duration (sec)
1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
J DM thJC C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRFI5210
(BR)
A
A
L
15V
+
V
DD
D.U.T
I
AS
0.01
p
DRIVER
Ω
R
V
G
-20V
DS
t
Fig 12a. Unclamped Inductive Test Circuit
I
AS
t
p
V
DSS
2000
I
TO P -8.6A
-15A
1600
1200
800
400
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting T , Junction Temperature (°C )
J
BOTTO M -21A
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
D
Fig 12b. Unclamped Inductive Waveforms
Q
G
-10V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T .
-3mA
I
G
Current Sampling Resistors
I
V
+
D
Fig 13b. Gate Charge Test Circuit
DS
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IRFI5210
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
**
• dv/dt controlled by R
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS*
R
G
* Reverse Polarity for P-Channel
** Use P-Channel Driver for P-Channel Measurements
Driver Gate Drive
P.W.
Period
-
D =
G
P.W.
Period
+
VGS=10V
[ ] ***
+
*
V
DD
-
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. ISDWaveform
Body Diode Forward
Current
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
*** V
= 5.0V for Logic Level and 3V Drive Devices
GS
di/dt
Diode Recovery
dv/dt
Fig 14. For P-Channel HEXFETS
V
DD
[ ]
I
[ ]
SD
Page 8
IRFI5210
A
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
10.60 (.417)
10.40 (.409)
16.00 (.630)
15.80 (.622)
1 2 3
13.70 (.540)
13.50 (.530)
1.40 (.055)
3X
1.05 (.042)
2.54 (.100)
2 X
3X
Part Marking Information
TO-220 Fullpak
E X A MP L E : T HIS IS A N I R F I840 G
W ITH ASSE MBL Y
L OT CO D E E 4 0 1
3.70 (.145)
3.20 (.126)
1.15 (.045)
MIN.
3.30 (.130)
3.10 (.122)
0.90 (.035)
0.70 (.028)
0.25 (.010)
3.40 (.133)
ø
3.10 (.123)
- A -
- B -
M
4.80 (.189)
4.60 (.181)
7.10 (.280)
6.70 (.263)
A M B
INTERNATIONAL
R E CTIFIE R
L OGO
ASSEMBLY
L O T C O DE
2.80 (.110)
2.60 (.102)
NOTES:
1 DIMENSIONING & TOLERANCING
PE R ANSI Y14.5M, 1982
2 CONTROLLING DIMENSION: INCH.
0.48 (.019)
3X
0.44 (.017)
2.85 (.112)
2.65 (.104)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOUR CE
MINIMUM CREEPAGE
DISTANCE BETW E EN
A-B-C-D = 4.80 (.189)
PART NUM BER
IRFI840G
E401 9245
DATE CODE
(YYWW )
YY = YEAR
WW = WEEK
C
D
A
B
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/ Data and specifications subject to change without notice. 3/98
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