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PD - 9.1611A
TO-220 FULLPAK
PRELIMINARY
IRFI1310N
HEXFET® Power MOSFET
l Advanced Process Technology
l Isolated Package
l High Voltage Isolation = 2.5KVRMS
l Sink to Lead Creepage Dist. = 4.8mm
l Fully Avalanche Rated
G
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial
applications. The moulding compound used provides
a high isolation capability and a low thermal resistance
between the tab and external heatsink. This isolation
is equivalent to using a 100 micron mica barrier with
standard TO-220 product. The Fullpak is mounted to
a heatsink using a single clip or by a single screw
fixing.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 24
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 17 A
I
DM
PD @TC = 25°C Power Dissipation 56 W
V
GS
E
AS
I
AR
E
AR
dv/d
t
T
J
T
STG
Pulsed Drain Current 140
Linear Derating Factor 0.37 W/°C
Gate-to-Source Voltage ± 20 V
Single Pulse Avalanche Energy 420 mJ
Avalanche Current 22 A
Repetitive Avalanche Energy 5.6 mJ
Peak Diode Recovery dv/dt 5.0 V/ns
Operating Junction and -55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
Junction-to-Case ––– 2.7
Junction-to-Ambient ––– 65
D
V
= 100V
DSS
R
DS(on)
= 0.036Ω
ID = 24A
S
°C
°C/W
3/16/98
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IRFI1310N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
C Drain to Sink Capacitance ––– 12 ––– ƒ = 1.0MHz
Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance ––– ––– 0.036 Ω VGS = 10V, ID = 13A
Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
Forward Transconductance 14 ––– ––– S VDS = 25V, ID = 22A
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 100V, VGS = 0V
µA
nA
VGS = -20V
Total Gate Charge ––– ––– 120 ID = 22A
Gate-to-Source Charge ––– ––– 15 nC VDS = 80V
Gate-to-Drain ("Miller") Charge ––– ––– 58 VGS = 10V, See Fig. 6 and 13
Turn-On Delay Time ––– 11 ––– VDD = 50V
Rise Time ––– 56 ––– ID = 22A
Turn-Off Delay Time ––– 45 ––– RG = 3.6Ω
ns
Fall Time ––– 40 ––– RD = 2.9Ω, See Fig. 10
4.5
Internal Drain Inductance
Internal Source Inductance ––– –––
––– –––
7.5
Between lead,
6mm (0.25in.)
nH
from package
and center of die contact
Input Capacitance ––– 1900 ––– VGS = 0V
Output Capacitance ––– 450 ––– VDS = 25V
Reverse Transfer Capacitance ––– 230 ––– ƒ = 1.0MHz, See Fig. 5
pF
D
G
S
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting T
RG = 25Ω, I
I
SD
TJ ≤ 175°C
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 13A, VGS = 0V
Reverse Recovery Time ––– 180 270 ns TJ = 25°C, IF = 22A
Reverse RecoveryCharge ––– 1.2 1.8 µC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
= 25°C, L = 1.0mH
J
= 22A. (See Figure 12)
AS
≤ 22A, di/dt ≤ 180A/µs, V
DD
≤ V
(BR)DSS
,
t=60s, ƒ=60Hz
Uses IRF1310N data and test conditions
24
140
showing the
A
p-n junction diode.
D
G
S
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IRFI1310N
1000
100
10
D
I , Drain-to-Source Current (A)
1
0.1 1 10 100
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20us PULSE WIDTH
T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
o
Fig 1. Typical Output Characteristics
1000
1000
100
10
D
I , Drain-to-Source Current (A)
1
0.1 1 10 100
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20us PULSE WIDTH
T = 175 C
J
V , Drain-to-Source Voltage (V)
DS
o
Fig 2. Typical Output Characteristics
3.0
I =
D
36A
100
10
D
I , Drain-to-Source Current (A)
1
4.0 5.0 6.0 7.0 8.0 9.0 10.0
V , Gate-to-Source Voltage (V)
GS
o
T = 25 C
J
o
T = 175 C
J
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V =
GS
o
10V
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IRFI1310N
3500
3000
2500
2000
1500
C, Capacitance (pF)
1000
500
0
1 10 100
V
=
0V,
GS
C
=
iss gs gd , ds
C
=
rss gd
C
=
oss ds gd
C
iss
C
oss
C
rss
V , Drain-to-Source Voltage (V)
DS
f = 1MHz
C
+ C
C
C
C SHORTED
+ C
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
20
I =
22A
D
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
0
0 20 40 60 80 100 120
V = 80V
DS
V = 50V
DS
V = 20V
DS
FOR TEST CIRCUIT
SEE FIGURE
Q , Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
100
10
1
SD
I , Reverse Drain Current (A)
V = 0 V
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V ,Source-to-Drain Voltage (V)
SD
GS
Fig 7. Typical Source-Drain Diode
Forward Voltage
100
10
D
I , Drain Current (A)I , Drain Current (A)
o
= 25 C
C
T T= 175 C
Single Pulse
1
1 10 100 1000
o
J
V , Drain-to-Source Voltage (V)
DS
10us
100us
1ms
10ms
Fig 8. Maximum Safe Operating Area
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IRFI1310N
25
20
15
10
D
I , Drain Current (A)
5
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
R
V
DS
V
GS
R
G
D
D.U.T.
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
+
V
DD
-
thJC
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
Thermal Response (Z )
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFI1310N
A
15V
DRIVER
+
-
R
V
G
20V
DS
L
D.U.T
I
AS
0.01
t
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
1000
TOP
800
600
V
DD
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting T , Junction Temperature ( C)
J
BOTTOM
9.0A
o
I
D
16A
22A
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
I
+
V
-
D
Fig 13b. Gate Charge Test Circuit
DS
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IRFI1310N
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
P.W.
Period
+
+
V
DD
-
VGS=10V
*
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. ISDWaveform
Body Diode Forward
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
Fig 14. For N-Channel HEXFETS
Current
di/dt
Diode Recovery
dv/dt
V
DD
I
SD
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IRFI1310N
A
A
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
10.60 (.417)
10.40 (.409)
16.00 (.630)
15.80 (.622)
1 2 3
13.70 (.540)
13.50 (.530)
1.40 (.055)
3X
1.05 (.042)
2.54 (.100)
2 X
3X
Part Marking Information
TO-220 Fullpak
EXAMPLE : THIS IS AN IRF1010
E X A MP L E : T H IS IS AN IRF I84 0 G
WITH ASSEMBLY
W IT H A S SE MB L Y
L OT C OD E E 4 0 1
LO T C O D E 9 B 1 M
3.70 (.145)
3.20 (.126)
1.15 (.045)
MIN.
3.30 (.130)
3.10 (.122)
0.90 (.035)
0.70 (.028)
0.25 (.010)
3.40 (.133)
ø
3.10 (.123)
- A -
- B -
M
4.80 (.189)
4.60 (.181)
7.10 (.280)
6.70 (.263)
A M B
INTERNA TIO NAL
INTERNATIONAL
RECTIFIER
R E CT IF IER
LO GO
L OG O
ASSEMBLY
ASSEMBLY
LO T C OD E
L O T C O DE
2.80 (.110)
2.60 (.102)
NOTES:
1 DIMENSIONING & TOLERANCING
PE R ANSI Y14.5M, 1982
2 CONTROLLING DIMENSION: INCH.
0.48 (.019)
3X
0.44 (.017)
2.85 (.112)
2.65 (.104)
IRF1010
IRFI840G
LEAD ASSIGNMENTS
1 - GATE
2 - DRA IN
3 - SOU RCE
MINIMUM CREEPAGE
DISTANCE BETW E EN
A-B-C-D = 4.80 (.189)
PART NUMBER
PART NUM BER
9246
9B 1M
E401 9245
DATE CODE
(YYW W)
DATE CODE
YY = YE AR
(YYWW )
YY = YEAR
WW = WEEK
WW = WEEK
C
D
A
B
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/ Data and specifications subject to change without notice. 3/98
Page 9
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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