Datasheet IRFF9230 Datasheet (Intersil)

IRFF9230

Data Sheet February 1999

-4.0A, -200V, 0.800 Ohm, P-Channel Power
MOSFET

This P-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanchemodeofoperation.Allof
these power MOSFETs are designed for applications such
as switching regulators, switching converters, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.

Formerly developmental type TA17512.

Ordering Information

PART NUMBER PACKAGE BRAND

IRFF9230 TO-205AF IRFF9230

NOTE: When ordering, use the entire part number.

File Number 2225.2

Features

• -4.0A, -200V

DS(ON)

= 0.800Ω

•r

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

Symbol

D

G

S

Packaging

DRAIN
(CASE)

JEDEC TO-205AF

SOURCE

GATE

4-114

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

IRFF9230

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

IRFF9230 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DS

D

DM

GS

D

-200 V

-200 V

-4.0 A

-16 A

±20 V

25 W

Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 W/oC

Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

AS

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

500 mJ

-55 to 150

300

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

On-State Drain Current (Note 2) I

D(ON)VDS

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Forward Transconductance (Note 2) g
Turn-On Delay Time t

d(ON)VDD

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t

Total Gate Charge

Q

g(TOT)VGS

(Gate to Source + Gate to Drain)
Gate to Source Charge Q
Gate to Drain “Miller” Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Internal Drain Inductance L

Internal Source Inductance L

Thermal Resistance Junction to Case R
Thermal Resistance

R

DSSID

DSS

GSS

fs

r

f

gs

gd

ISS
OSS
RSS

D

S

θJC

θJA

= -250µA, VGS = 0V, (Figure 10) -200 - - V

= VDS, ID = -250µA -2 - -4 V
VDS = Rated BV
VDS = 0.8 x Rated BV

> I

D(ON)

, VGS = 0V - - -25 µA

DSS

, VGS = 0V, TC = 125oC - - -250 µA

DSS

x r

DS(ON)MAX

, VGS = -10V -4.0 - - A

VGS = ±20V - - ±100 nA

= -2.0A, VGS = -10V, (Figures 8, 9) - 0.5 0.800 Ω

VDS > I

= 0.5BV
RL = 2.5Ω for BV
RL = 18.7Ω for BV
(Figures 17, 18) MOSFET Switching Times are
Essentially Independent of Operating

D(ON)

x r

DS(ON)MAX

, I

DSS

D

DSS

DSS

, ID = -2.0A, (Figure 12) 2.2 3.5 - S

≈ -4.0A, R

= -200V

= -150V

= 9.1Ω,

G

-3050ns

- 50 100 ns

- 50 100 ns

-4080ns

Temperature

= -10V, ID = -4.0A, VDS = 0.8 x Rated BV
I

= -1.5mA, (Figures 14, 19, 20)

G(REF)

Gate Charge is Essentially Independent of
Operating Temperature

DSS,

-3145nC

-18-nC

-13-nC

VDS = -25V, VGS = 0V, f = 1MHz, (Figure 11) - 550 - pF

- 170 - pF

-50-pF

Measured From the Drain
Lead, 5mm (0.2in) From
Package to Center of Die

Measured From the Source
Lead, 5mm (0.2in) From
Header to Source Bonding
Pad

Modified MOSFET
Symbol Showing the In­ternal Devices
Inductances

D

L

D

G

L

S

S

- 5.0 - nH

-15-nH

- - 5.0

o

C/W

Typical Socket Mount - - 175oC/W

Junction to Ambient

4-115

IRFF9230

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I
Pulse Source to Drain Current

I

SD
SM

(Note 3)

Source to Drain Diode Voltage (Note 2) V
Reverse Recovery Time t
Reverse Recovery Charge Q

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD= 50V, starting TJ= 25oC, L = 46.9mH, RG= 25Ω, peak IAS= 4.0A (Figures 15, 16).

Modified MOSFET Symbol
Showing the Integral
Reverse P-N Junction

D

- - -4.0 A

- - -16 A

Rectifier

G

S

TC = 25oC, ISD = -4.0A, VGS = 0V, (Figure 13) - - -1.5 V

SD

TJ = 150oC, ISD = -4.0A, dISD/dt = 100A/µs - 400 - ns

rr

TJ = 150oC, ISD = -4.0A, dISD/dt = 100A/µs - 2.6 - µC

RR

Typical Performance Curves Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TC, CASE TEMPERATURE (oC)

125

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

1

0.5

0.2

0.1

0.1

, NORMALIZED

θJC

Z

TRANSIENT THERMAL IMPEDANCE

0.01
10

0.05

0.02

0.01

-5

SINGLE PULSE

-4

10

-3

10

t1, RECTANGULAR PULSE DURATION (s)

-5

-4

-3

-2

, DRAIN CURRENT (A)

D

I

-1

0

25 75 125

50 100

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-2

10

-1

10

1/t2

x R

θJC

1

150

t

1

t

2

+ T

θJC

C

10

4-116

FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE

IRFF9230

Typical Performance Curves Unless Otherwise Specified (Continued)

-100

-10

-1

, DRAIN CURRENT (A)

D

I

T
T
SINGLE PULSE

-0.1

OPERATION IN THIS AREA
IS LIMITED BY r

= 25oC

C

= MAX RATED

J

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

10µs

100µs

1ms

10ms

100ms

DC

-10-1

-100

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

-15
PULSE DURATION = 80µs

-12

-9

-6

, DRAIN CURRENT (A)

D

I

-3

0

0

-2
VDS, DRAIN TO SOURCE VOLTAGE (V)

-4 -6 -10

VGS = -10V

-9V

-8V

-8

-7V

-6V

-5V

-4V

-1000

-15
VGS = -10V

-12

-9

-6

, DRAIN CURRENT (A)

D

I

-3

0

0 -10 -20 -30 -40

VGS = -9V

VGS = -8V

VGS = -7V

80µs PULSE TEST

VGS = -6V

VGS = -5V

VGS = -4V

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 5. OUTPUT CHARACTERISTICS

-15
PULSE DURATION = 80µs

≥ I

D(ON)

x r

V

GS

V

DS

-12

-9

-6

-3

, ON-STATE DRAIN CURRENT (A)

D(ON)

I

0

0 -2-4 -6-8-10

MAX

DS(ON)

TJ = 125oC

TJ = 25oC

TJ = -55oC

, GATE TO SOURCE VOLTAGE (V)

-50

FIGURE 6. SATURATION CHARACTERISTICS

2.0
PULSE DURATION = 2µs

1.6

1.2

VGS= -10V

0.8

, DRAIN TO SOURCE

ON RESISTANCE (Ω)

DS(ON)

r

0.4

0

0

-5 -10 -15 -20
ID, DRAIN CURRENT (A)

VGS= -20V

NOTE: Heating effect of 2µs pulse is minimal.

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

4-117

-25

FIGURE 7. TRANSFER CHARACTERISTICS

2.5
VGS = -10V, ID = -2A

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-40 0 40
, JUNCTION TEMPERATURE (oC)

T

J

80

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

120

160

IRFF9230

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25
ID = -250µA

1.15

1.05

0.95

BREAKDOWN VOLTAGE

0.85

NORMALIZED DRAIN TO SOURCE

0.75

-40 0 40
, JUNCTION TEMPERATURE (oC)

T

J

80 120 160

FIGURE 10. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

7.0
PULSE DURATION = 80µs

5.6

4.2

TJ = -55oC

TJ = 25oC

2000

VGS= 0V, f = 1MHz
C

= CGS + C

1600

1200

800

C, CAPACITANCE (pF)

400

0

0

ISS

C

RSS

C

OSS

= C

≈ CDS+ C

GD

GD

GD

C

ISS

C

-20

RSS

-30 -40

C

OSS

-10
, DRAIN TO SOURCE VOLTAGE (V)

V

DS

-50

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

-100

-10

TJ = 150oC

2.8

, TRANSCONDUCTANCE (S)

1.4

fs

g

0

0 -3 -6 -9 -12

ID, DRAIN CURRENT (A)

TJ = 125oC

-15

-1.0

, SOURCE TO DRAIN CURRENT (A)

SD

I

-0.1

-0.4
V

SD

TJ = 25oC

-0.8 -1.4

-1.0 -1.2 -1.6 -1.8-0.6

, SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

0

-5

-10

, GATE TO SOURCE (V)

GS

V

-15

0 8 16243240

VDS = -160V

= -100V

V

DS

= -40V

V

DS

, TOTAL GATE CHARGE (nC)

Q

g(TOT)

ID = -4A

4-118

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

IRFF9230

Test Circuits and Waveforms

V

DS

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V

V

GS

t

P

AS

L

R

G

-

V

DD

+

DUT

I

AS

0.01Ω

0

V

DD

I

AS

t

P

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

BV

t

AV

DSS

V

DS

t

ON

t

d(ON)

t

R

L

DUT

R

V

GS

G

-

V

DD

+

0

V

DS

V

GS

0

10%

r

10%

90%

50%

PULSE WIDTH

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

-V

DS

D

(ISOLATED
SUPPLY)

DUT

0

V

DS

Q

gs

Q

gd

12V

BATTERY

0.2µF

50kΩ

CURRENT

REGULATOR

0.3µF

t

d(OFF)

V

GS

t

OFF

50%

90%

90%

t

f

10%

Q

g(TOT)

S

CURRENT

I

D

SAMPLING

DUT

+V

DS

V

DD

0

I

G(REF)

G

0

I

G(REF)

IG CURRENT

SAMPLING

RESISTOR RESISTOR

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

4-119

IRFF9230

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rightsof third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

4-120

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]