These are advanced power MOSFETs designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. The y are P-Channel
enhancement mode silicon gate power field effect transistors
designed for applications such as switching regulators ,
switchingconverters,motor drivers, relay drivers and drivers for
high power bipolar switching transistors requiring high speed
and low gate drivepower.Thesetypescan be operated directly
from integrated circuits.
Formerly develpomental type TA17502.
Ordering Information
PART NUMBERPACKAGEBRAND
IRFF9220TO-205AFIRFF9220
NOTE: When ordering, use the entire part number.
Packaging
JEDEC TO-205AF
Features
• -2.5A, -200V
DS(ON)
= 1.5Ω
•r
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
Symbol
D
G
S
DRAIN
(CASE)
SOURCE
GATE
4-107
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
290mJ
-55 to 150
300
o
C
o
C
NOTE:
1. TJ= 25oC to 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
On-State Drain Current (Note 2)I
D(ON)VDS
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 2)r
DS(ON)ID
Forward Transconductance (Note 2)g
Turn-On Delay Timet
d(ON)VDD
Rise Timet
Turn-Off Delay Timet
d(OFF)
Fall Timet
Total Gate Charge
Q
g(TOT)VGS
(Gate to Source + Gate to Drain)
Gate to Source ChargeQ
Gate to Drain “Miller” ChargeQ
Input CapacitanceC
Output CapacitanceC
Reverse Transfer CapacitanceC
Internal Drain InductanceL
Internal Source InductanceL
Thermal Resistance Junction to CaseR
Thermal Resistance
R
DSSID
DSS
GSS
fs
r
f
gs
gd
ISS
OSS
RSS
D
S
θJC
θJA
= -250µA, VGS = 0V, (Figure 10)-200--V
= VDS, ID = -250µA-2--4V
VDS = Rated BV
VDS = 0.8 x Rated BV
> I
D(ON)
, VGS = 0V---25µA
DSS
, VGS = 0V, TC = 125oC---250µA
DSS
x r
DS(ON)MAX
, VGS = -10V-2.5--A
VGS = ±20V--±100nA
= 1.5A, VGS = -10V, (Figures 8, 9)-1.01.5Ω
VDS > I
D(ON)
x r
DS(ON)MAX
, ID = 1.5A,
11.8-S
(Figure 12)
= 0.5 x Rated BV
RL = 38.5Ω for BV
RL = 28.5Ω for BV
(Figures 17, 18) MOSFET Switching Times are
Essentially Independent of Operating
Temperature
= -10V, ID = -2.5A, VDS = 0.8 x Rated BV
I
= -1.5mA, (Figures 14, 19, 20)
G(REF)
Gate Charge is Essentially Independent of
Operating Temperature
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
0
-5
-10
-15
, GATE TO SOURCE VOLTAGE (V)
GS
V
-20
0 4 8 121620
Q
VDS = -100V
VDS = -60V
VDS = -40V
, TOTAL GATE CHARGE (nC)
g(TOT)
ID = -2.5A
4-111
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Page 6
IRFF9220
Test Circuits and Waveforms
V
DS
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V
V
GS
t
P
AS
L
R
G
-
V
DD
+
DUT
I
AS
0.01Ω
0
V
DD
I
AS
t
P
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
BV
t
AV
DSS
V
DS
t
ON
t
d(ON)
t
R
L
DUT
R
V
GS
G
-
V
DD
+
0
V
DS
V
GS
0
r
10%
90%
10%
50%
PULSE WIDTH
FIGURE 17. SWITCHING TIME TEST CIRCUITFIGURE 18. RESISTIVE SWITCHING WAVEFORMS
-V
DS
D
(ISOLATED
SUPPLY)
DUT
0
V
DS
Q
gs
Q
gd
12V
BATTERY
0.2µF
50kΩ
CURRENT
REGULATOR
0.3µF
t
d(OFF)
V
GS
t
OFF
50%
90%
90%
t
f
10%
Q
g(TOT)
S
CURRENT
I
D
SAMPLING
DUT
+V
DS
V
DD
0
I
G(REF)
G
0
I
G(REF)
IG CURRENT
SAMPLING
RESISTORRESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUITFIGURE 20. GATE CHARGE WAVEFORMS
4-112
Page 7
IRFF9220
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
4-113
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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