Datasheet IRFF120 Datasheet (Intersil)

IRFF120

Data Sheet March 1999

6.0A, 100V, 0.300 Ohm, N-Channel
Power MOSFET

This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.

Formerly developmental type TA09594.

Ordering Information

PART NUMBER PACKAGE BRAND

IRFF120 TO-205AF IRFF120

NOTE: When ordering, use the entire part number.

File Number 1563.3

Features

• 6.0A, 100V

•r

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount

= 0.300Ω

DS(ON)

Components to PC Boards”

Symbol

D

G

Packaging

JEDEC TO-205AF

DRAIN
(CASE)

S

SOURCE

GATE

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

IRFF120

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

IRFF120 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DS

D

DM

GS

D

100 V
100 V

6.0 A
24 A

±20 V

20 W

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.16 W/oC

Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,T

AS

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

36 mJ

-55 to 150

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

On-State Drain Current (Note 2) I

D(ON)VDS

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Forward Transconductance (Note 2) g
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge

Q

g(TOT)VGS

(Gate to Source + Gate to Drain)
Gate to Source Charge Q
Gate to Drain (“Miller”) Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Internal Drain Inductance L

Internal Source Inductance L

Thermal Resistance, Junction to Case R
Thermal Resistance, Junction to Ambient R

DSSID

DSS

GSS

fs

r

f

gs
gd

ISS
OSS
RSS

D

S

θJC

θJA

= 250µA, VGS = 0V (Figure 10) 100 - - V

= VDS, ID = 250µA 2.0 - 4.0 V
VDS = Rated BV
VDS = 0.8 x Rated BV

> I

D(ON)

, VGS = 0V - - 25 µA

DSS

, VGS = 0V, TC = 125oC - - 250 µA

DSS

x r

DS(ON)MAX

, VGS = 10V 6.0 - - A

VGS = ±20V - - ±100 nA

= 3.0A, VGS = 10V (Figures 8, 9) - 0.25 0.300 Ω
VDS > I
VDD≅ 0.5 x Rated BV

VGS=10V (Figures 17, 18), RL=8Ω forV
RL = 6.3Ω for V
Times are Essentially Independent of Operating
Temperatures

= 10V, ID = 6.0A, VDS = 0.8 x Rated BV

D(ON)

x r

DS(ON)MAX

DSS

, ID = 3.0A (Figure 12) 1.5 2.9 - S

, ID= 6.0A, RG = 9.1Ω,

DSS

= 40V, MOSFET Switching

DSS

= 50V,

DSS

-2040ns

-3770ns

- 50 100 ns

-3570ns

-1015nC
(Figures 14, 19, 20) Gate Charge is Essentially
Independent of Operating Temperature

- 6.0 - nC

- 4.0 - nC
VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 450 - pF

-20-pF

-50-pF
Measured from the Drain

Lead, 5.0mm (0.2in) from
Header to Center of Die

Measured from the Source
Lead, 5.0mm (0.2in) from
Header to Source Bonding
Pad

Modified MOSFET
Symbol Showing the
Internal Devices
Inductances

D

L

D

G

L

S

S

- 5.0 - nH

-15-nH

- - 6.25oC/W
Free Air Operation - - 175oC/W

2

IRFF120

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I
Pulse Source to Drain Current (Note 3) I

Source to Drain Diode Voltage (Note 2) V
Reverse Recovery Time t
Reverse Recovery Charge Q
Forward Turn-On Time t

SD
SM

SD
rr
RR

ON

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD= 25V, starting TJ= 25oC, L = 1.5mH, RG= 25Ω, peak IAS= 6.0A (Figures 15, 16).

Modified MOSFET
Symbol Showing the
Integral Reverse P-N

D

- - 6.0 A

- - 24 A

Junction Rectifier

G

S

TJ = 25oC, ISD = 6.0A, VGS = 0V (Figure 13) - - 2.5 V
TJ = 150oC, ISD = 6.0A, dISD/dt = 100A/µs - 230 - ns
TJ = 150oC, ISD = 6.0A, dISD/dt = 100A/µs - 1.0 - µC
Intrinsic Turn-on Time is Negligible, Turn-On

Speed is Substantially controlled by LS + L

D

--- -

Typical Performance Curves Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 50 100 150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

1.0

0.5

0.2

0.1

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01
10

0.05

0.02

0.01

-5

SINGLE PULSE

-4

10

-3

10

t1, RECTANGULAR PULSE DURATION (s)

6.0

4.8

3.6

2.4

, DRAIN CURRENT (A)

D

I

1.2

0

25 50 75 100

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-2

10

-1

10

1/t2

x R

θJC

1

+ T

150

C

10

125

1

t

2

θJC

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

3

IRFF120

Typical Performance Curves Unless Otherwise Specified (Continued)

50.0

10.0

1.0

, DRAIN CURRENT (A)

D

I

0.1

OPERATION IN THIS
AREA IS LIMITED
BY r

DS(ON)

TJ= MAX RATED

1.0 10.0 100.0 200.0
, DRAIN TO SOURCE VOLTAGE (V)

V

DS

10µs
100µs

1ms

10ms
100ms

DC

20

16

12

8

, DRAIN CURRENT (A)

D

I

4

0

01020304050

VGS = 10V

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

80µs PULSE TEST

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

10

80µs PULSE TEST

8

6

VGS = 10V

VGS = 9V

VGS = 8V

VGS = 7V

VGS = 6V

20

VDS > I
80µs PULSE TEST

16

12

D(ON)

x r

DS(ON)MAX

125oC

25oC

-55oC

VGS = 9V

VGS = 8V

VGS = 7V

VGS = 6V

VGS = 5V

VGS = 4V

4

, DRAIN CURRENT (A)

D

I

2

0

0

1

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 5V

VGS = 4V

23 5

4

8

4

, ON-STATE DRAIN CURRENT (A)

D(ON)

I

0

02 6

VGS, GATE TO SOURCE VOLTAGE (V)

4 810

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

0.8

0.6

0.4

, DRAIN TO SOURCE

ON RESISTANCE (Ω)

0.2

DS(ON)

r

0

2µs PULSE TEST

VGS = 10V

0

10

VGS = 20V

20

ID, DRAIN CURRENT (A)

30 40

2.50

2.00

1.50

1.00

ON REISITANCE

0.50

NORMALIZED DRAIN TO SOURCE

VGS = 10V

= 3A

I

D

0

-40 0 40
T

, JUNCTION TEMPERATURE (oC)

J

80

120

NOTE: Heating effect of 2µs pulse is minimal.

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

4

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

IRFF120

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25
ID = 250µA

1.15

1.05

0.95

BREAKDOWN VOLTAGE

0.85

NORMALIZED DRAIN TO SOURCE

0.75

-40 0 40
T

, JUNCTION TEMPERATURE (oC)

J

80

120

FIGURE 10. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

5

80µs PULSE TEST

4

3

2

1

, TRANSCONDUCTANCE (S)

fs

g

0

0481216

-55oC

o

25

ID, DRAIN CURRENT (A)

C

125oC

20

1000

800

600

400

C, CAPACITANCE (pF)

200

0

C

ISS

C

OSS

C

RSS

10 20

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

30 40 500

= 0V, f = 1MHz

V

GS

C

= CGS + C

ISS

C

= C

RSS

C

≈ CDS+ C

OSS

GD

GD

GD

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

100

5

2

10

5

2

, SOURCE TO DRAIN CURRENT (A)

SD

I

1.0
0231

150oC

25oC

VSD, SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20

ID = 6A

15

VDS = 20V

10

, GATE TO SOURCE (V)

5

GS

V

0

0481216

, TOTAL GATE CHARGE (nC)

Q

g(TOT)

VDS = 50V

VDS = 80V

20

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

5

Test Circuits and Waveforms

IRFF120

BV

DSS

P

VARY t

TO OBTAIN

P

REQUIRED PEAK I

AS

V

DS

t

L

R

G

+

V

DD

-

I

AS

DUT

V

0V

GS

t

P

I

AS

0.01Ω

0

t

AV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORM

t

ON

t

d(ON)

t

V

R

L

+

V

R

G

DD

-

DUT

V

GS

DS

0

V

GS

0

90%

10%

r

10%

50%

PULSE WIDTH

t

d(OFF)

90%

V

t

DS

OFF

50%

t

f

10%

V

DD

90%

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

V

DS

D

S

CURRENT

I

D

SAMPLING

(ISOLATED
SUPPLY)

SAME TYPE
AS DUT

DUT

V

DS

V

DD

Q

g(TOT)

Q

gd

Q

gs

V

DS

0

I

G(REF)

0

FIGURE 20. GATE CHARGE WAVEFORMS

12V

BATTERY

0

CURRENT

REGULATOR

0.2µF

50kΩ

0.3µF

G

I

G(REF)

IG CURRENT

SAMPLING

RESISTOR RESISTOR

FIGURE 19. GATE CHARGE TEST CIRCUIT

6

V

GS

IRFF120

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