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PD - 93985
REPETITIVE AVALANCHE AND dv/dt RATED IRFE320
HEXFETTRANSISTORS JANTX2N6792U
SURFACE MOUNT (LCC-18) JANTXV2N6792U
[REF:MIL-PRF-19500/555]
400V, N-CHANNEL
Product Summary
Part Number BVDSS R DS(on) I D
IRFE320 400V 1.8Ω 1.8A
The leadless chip carrier (LCC) package represents the
logical next step in the continual evolution of surface
LCC-18
mount technology. Desinged to be a close replacement
for the TO-39 package, the LCC will give designers the
extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by
increasing the size of the bottom source pad, thereby
enhancing the thermal and electrical performance. The
lid of the package is grounded to the source to reduce
RF interference.
Features:
! Surface Mount
! Small Footprint
! Alternative to TO-39 Package
! Hermetically Sealed
! Dynamic dv/dt Rating
! Avalanche Energy Rating
! Simple Drive Requirements
! Light Weight
Absolute Maximum Ratings
Parameter Units
ID @ VGS = 10V, TC = 25°C Continuous Drain Current 1. 8
ID @ VGS = 10V, TC = 100°C Continuous Drain Current 1. 1
I
DM
PD @ TC = 25°C Max. Power Dissipation 14 W
V
GS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt ➂ 4.0
T
J
T
STG
Pulsed Drain Current ➀ 7.2
Linear Derating Factor 0.11 W/°C
Gate-to-Source Voltage ±20 V
Single Pulse Avalanche Energy ➁ 0.185 mJ
Avalanche Current ➀ -A
Repetitive Avalanche Energy ➀ -m J
Operating Junction -55 to 150
Storage Temperature Range
Pckg. Mounting Surface Temp. 300 (for 5 S)
Weight 0.42(typical) g
A
V/ns
o
C
For footnotes refer to the last page
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1/16/01
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IRFE320
Electrical Characteristics @ Tj = 25°C (Unless Otherwise Specified)
Parameter Min Typ Max Units Test Conditions
BV
∆ BV
R
V
g
I
I
I
Q
Q
Q
t
t
t
t
L
C
C
C
DSS
GSS
GSS
d(on)
r
d(off)
f
DSS
DSS
DS(on)
GS(th)
fs
g
gs
gd
S + LD
iss
oss
rss
Drain-to-Source Breakdown Voltage 40 0 — — V VGS = 0V, ID = 1.0mA
/∆ T
Temperature Coefficient of Breakdown — 0.37 — V/°C Reference to 25°C, ID = 1.0mA
J
Voltage
Static Drain-to-Source On-State — — 1. 8 VGS = 10V, I
Resistance — — 2.07 V
Gate Threshold Voltage 2.0 — 4.0 V VDS = VGS, ID =250µA
Forward Transconductance 1. 0 — — S ( ) V
Zero Gate Voltage Drain Current — — 2 5 VDS=320V, VGS=0V
— — 250 VDS =320V
Gate-to-Source Leakage Forward — — 100 VGS = 20V
Gate-to-Source Leakage Reverse — — -100 VGS = -20V
Total Gate Charge — — 15.5 VGS =10V, ID= 1.8A
Gate-to-Source Charge — — 2. 6 nC VDS =200V
Gate-to-Drain (‘Miller’) Charge — — 8. 3
Turn-On Delay Time — — 40 VDD =200V, ID =1.8A,
Rise Time — — 3 5 R
Turn-Off Delay Time — — 60
Fall Time — — 35
Total Inductance — 6 .1 —
Input Capacitance — 350 VGS = 0V, VDS = 25V
Output Capacitance — 100 — pF f = 1.0MHz
Reverse Transfer Capacitance — 4 5 —
Ω
Ω
µA
VGS = 0V, TJ = 125°C
nA
ns
nH
= 1.1A➃
D
=10V, I
GS
> 15V, I
DS
Measured from the center of
drain pad to center of source
pad
=7.5Ω
G
=1.8A ➃
D
=1.1A➃
DS
Source-Drain Diode Ratings and Characteristics
Parameter Min Typ Max Units Test Conditions
I
Continuous Source Current (Body Diode) — — 1.8
S
I
Pulse Source Current (Body Diode) ➀ — — 7.2
SM
V
Diode Forward Voltage — — 1. 4 V Tj = 25°C, IS = 1.8A, V
SD
t
Reverse Recovery Time — — 6 50 nS Tj = 25°C, I
rr
Q
Reverse Recovery Charge — — 5 .0 µc V
RR
t
Forward Turn-On Time Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by L
on
A
= 0V ➃
= 1.8A, di/dt ≤ 100A/µs
F
DD
GS
≤ 50V ➃
S
Thermal Resistance
Parameter Min Typ Max Units Test Conditions
R
thJC
R
thJ-PCB
For footnotes refer to the last page
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Junction to Case — — 9. 1
Junction to PC Board — — 26""" Soldered to a copper clad PC board
°C/W
+ LD.
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IRFE320
Fig 2. Typical Output Characteristics Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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IRFE320
13 a& b
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
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Fig 9. Maximum Drain Current Vs.
Case Temperature
IRFE320
R
D.U.T.
t
d(off)tf
D
V
DS
V
GS
R
G
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)tr
Fig 10b. Switching Time Waveforms
+
V
DD
-
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFE320
15V
DRIVER
+
-
R
V
G
10V
20 V
DS
L
D.U.T
I
AS
0.01
t
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
Q
GD
V
DD
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
DS
-
V
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
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GS
3mA
I
G
Current Sampling Resistors
I
D
Fig 13b. Gate Charge Test Circuit
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IRFE320
Foot Notes:
➀ Repetitive Rating; Pulse width limited by
maximum junction temperature.
➁ V
= 50V, starting TJ = 25°C,
DD
Peak IL = 1.8A,
➃ Pulse width ≤ 300 µ s; Duty Cycle ≤ 2%
Case Outline and Dimensions — LCC-18
➂ I
≤ 1.8A, di/dt ≤ 65A/µ s,
SD
V
≤ 400V, TJ ≤ 150°C
DD
Suggested RG =7.5 Ω
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Data and specifications subject to change without notice. 1/01
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