Datasheet IRFD9120 Datasheet (Intersil)

IRFD9120

Data Sheet July 1999

1.0A, 100V, 0.6 Ohm, P-Channel Power
MOSFET

This advanced power MOSFET is designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. These are
P-Channel enhancement mode silicon gate power field
effecttransistors designed for applications such as switching
regulators, switching convertors, motor drivers, relay drivers
and drivers for high power bipolar switching transistors
requiring high speed and low gate drive power. These types
can be operated directly from integrated circuits.

Formerly developmental type TA17501.

Ordering Information

PART NUMBER PACKAGE BRAND

IRFD9120 HEXDIP IRFD9120

NOTE: When ordering, use the entire part number.

File Number

Features

• 1.0A, 100V

DS(ON)

= 0.6Ω

•r

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

Symbol

D

G

S

2285.3

Packaging

HEXDIP

DRAIN

GATE

SOURCE

4-45

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

IRFD9120

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

IRFD9120 UNITS

Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DS

D

DM

GS

D

-100 V

-100 V

-1.0 A

-8.0 A
±20 V

1.0 W

Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008 W/oC

Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

AS

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

370 mJ

-55 to 150

300
260

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

On-State Drain Current (Note 2) I

D(ON)

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Forward Transconductance (Note 2) g
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge

Q

g(TOT)VGS

(Gate to Source + Gate to Drain)
Gate to Source Charge Q
Gate to Drain “Miller” Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Internal Drain Inductance L

Internal Source Inductance L

Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

fs

r

f

gs
gd

ISS
OSS
RSS

D

S

θJA

= -250µA, VGS = 0V, (Figure 9) -100 - - V

= VDS, ID = -250µA -2 - -4 V
VDS = Rated BV
VDS = 0.8 x Rated BV
VDS > I

D(ON)

, VGS = 0V - - -25 µA

DSS

, VGS = 0V, TC = 125oC - - -250 µA

DSS

x r

DS(ON) MAX

, VGS = -10V -1.0 - - A

VGS = ±20V - - ±500 nA

= -0.8A, VGS = -10V, (Figures 7, 8) - 0.5 0.6 Ω
VDS < 50V, ID = -0.8A (Figure 11) 0.8 1.2 - S
VDD = 0.5 x Rated BV

RG = 9.1Ω, VGS = -10V, (Figures 16, 17)
RL = 50Ω for VDD= -50V
MOSFET Switching Times are Essentially Indepen­dent of Operating Temperature

= -10V, ID = -1.0A, VDS = 0.8 x Rated BV

, ID = -1.0A,

DSS

DSS

-2550 ns

- 50 100 ns

- 50 100 ns

- 50 100 ns

-1620nC
(Figures 13, 18, 19)
Gate ChargeisEssentiallyIndependent of Operating
Temperature

-9- nC

-7- nC
VDS = -25V, VGS = 0V, f = 1MHz, (Figure 10) - 300 - pF

- 200 - pF

-50- pF
Measured From the Drain

Lead,2.0mm(0.08in) From
Header to Center of Die

MeasuredFrom the Source
Lead,2.0mm(0.08in) From
Header to Source Bonding
Pad

Modified MOSFET
Symbol Showing the In­ternal Devices
Inductances

D

L

D

G

L

S

S

- 4.0 - nH

- 6.0 - nH

Typical Socket Mount - - 120oC/W

4-46

IRFD9120

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I
Pulse Source to Drain Current

SD

I

SDM

(Note 3)

Source to Drain Diode Voltage (Note 2) V

SD

Reverse Recovery Time t
Reverse Recovery Charge Q

RR

NOTES:

2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature.

4. VDD= 25V, starting TJ= 25oC, L = 555mH, RG= 25Ω, Peak IAS= 1.0A (Figures 14, 15).

ModifiedMOSFETSymbol
Showing the Integral
Reverse P-N Junction
Diode

G

TC = 25oC, ISD = -1.0A, VGS = 0V, (Figure 12) - - -1.5 V
TJ = 150oC, ISD = -4.0A, dISD/dt = 100A/µs - 150 - ns

rr

TJ = 150oC, ISD = -4.0A, dISD/dt = 100A/µs - 0.9 - µC

D

S

- - -1.0 A

- - -8.0 A

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZEDPOWER DISSIPATIONvs AMBIENT

TEMPERATURE

10

1

0.1
OPERATION IN THIS AREA

IS LIMITED BY r

TC = 25oC

, DRAIN TO SOURCE CURRENT (A)

T

= MAX RATED

J

0.01

DS

I

SINGLE PULSE

DS(ON)

101

VDS, DRAIN TO SOURCE VOLTAGE (V)

100

10µs

100µs
1ms

10ms

100ms

DC

-1.0

-0.8

-0.6

-0.4

, DRAIN CURRENT (A)

D

I

-0.2

0

25 75 125

50 100

TA, AMBIENT TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAINCURRENTvs

AMBIENT TEMPERATURE

-5

-4

-3

-2

-1

, DRAIN TO SOURCE CURRENT (A)

DS

I

0

0 -10 -20 -30 -40

VGS = -7V

VGS = -10V

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

VGS = -6V

VGS = -5V

VGS = -4V

150

-50

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. OUTPUT CHARACTERISTICS

4-47

IRFD9120

Typical Performance Curves

-5

-4

-3

-2

-1

, DRAIN TO SOURCE CURRENT (A)

DS

I

0

0

FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS

1.6

1.2

VGS = -8V

VGS = -9V

VGS = -10V

-1
VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = -6V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

VGS = -5V

VGS = -4V

-2 -3 -5

Unless Otherwise Specified (Continued)

-5

VGS = -7V

-4

-3

-2

-1

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

-4

0

-2 -3 -4 -5 -6 -7

2.2

1.8

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VDS≥ I

VGS = -10V, ID = -8A
PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX.

D(ON)

x r

V

GS

MAX.

DS(ON)

TJ = 125oC

, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

TJ = 25oC

0.8

, DRAIN TO SOURCE

0.4

DS(ON)

ON-STATE RESISTANCE (Ω)

r

0

0-2-4-6-8

VGS = -10V

VGS = -20V

ID, DRAIN CURRENT (A)

NOTE: Heating effect of 2µs pulse is minimal.

FIGURE 7. DRAIN TOSOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

1.25

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

1.15

1.05

0.95

BREAKDOWN VOLTAGE

0.85

NORMALIZED DRAIN TO SOURCE

0.75

-40 0 40
T

, JUNCTION TEMPERATURE (oC)

J

80 120

1.4

1.0

ON RESISTANCE

0.6

NORMALIZED DRAIN TO SOURCE

0.2

-40 0 40
T

, JUNCTION TEMPERATURE (oC)

J

80

FIGURE 8. NORMALIZED DRAIN TOSOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

500

400

300

200

C, CAPACITANCE (pF)

100

0

0

C

ISS

C

OSS

C

RSS

-10
V

DS

-20

, DRAIN TO SOURCE VOLTAGE (V)

VGS= 0V, f = 1MHz
C

= CGS + C

ISS

C

RSS

C

OSS

-30 -40

= C

≈ C

GD
DS

120

+ C

GD

GD

-50

FIGURE 9. NORMALIZED DRAINTO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

4-48

FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

IRFD9120

Typical Performance Curves

3

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

2

1

, TRANSCONDUCTANCE (S)

fs

g

0

0

-2 -4 -6

ID, DRAIN CURRENT (A)

Unless Otherwise Specified (Continued)

-100

-10

TJ = -55oC

= 25oC

T

J

= 125oC

T

J

-1.0

, SOURCE TO DRAIN CURRENT (A)

SD

I

-0.1

-0.4

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

TJ = 150oC

TJ = 25oC

-0.8 -1.4

V

SD

-1.0 -1.2 -1.6 -1.8-0.6

, SOURCE TO DRAIN VOLTAGE (V)

FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE

0

-5

ID = -4A

-10

-15

, GATE TO SOURCE VOLTAGE (V)

GS

V

-20

FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE

fd

Test Circuits and Waveforms

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V
V

GS

t

P

AS

R

G

VDS = -80V

VDS = -50V
V

= -20V

DS

0481216

Q

, TOTAL GATE CHARGE (nC)

g(TOT)

V

DS

L

+

V

DD

-

DUT

I

AS

0.01Ω

0

V

DD

I

AS

20

t

AV

V

t

P

BV

DSS

DS

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

4-49

IRFD9120

Test Circuits and Waveforms

DUT

R

V

GS

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

12V

BATTERY

0.2µF

G

50kΩ

CURRENT

REGULATOR

0.3µF

(Continued)

R

L

D

-

V

DD

+

-V

DS

(ISOLATED
SUPPLY)

DUT

t

ON

t

d(ON)

t

50%

r

10%

90%

PULSE WIDTH

Q

gd

V

DS

0

V

DS

V

GS

0

0

10%

Q

gs

t

d(OFF)

V

GS

t

OFF

50%

90%

90%

t

f

10%

Q

G

0

I

G(REF)

IG CURRENT

SAMPLING

RESISTOR RESISTOR

DUT

S

CURRENT

I

D

SAMPLING

+V

DS

V

DD

0

I

G(REF)

g(TOT)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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4-50