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PD - 91818A
SMPS MOSFET
IRFBL12N50A
HEXFET® Power MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
Benefits
l Low Gate Charge Qg Results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 13
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 8.2 A
I
DM
PD @TC = 25°C Power Dissipation 180 W
V
GS
dv/dt Peak Diode Recovery dv/dt 3.1 V/ns
T
J
T
STG
Pulsed Drain Current 52
Linear Derating Factor 1.4 W/°C
Gate-to-Source Voltage ± 30 V
Operating Junction and -55 to + 150
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
V
DSS
R
DS(on)
max I
500V 0.45Ω 13A
Super-D2Pak
TM
D
°C
Typical SMPS Topologies
l Active Clamped Forward
l Main Switch
Notes through are on page 8
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IRFBL12N50A
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 84 ––– VGS = 0V, VDS = 0V to 400V
oss
Avalanche Characteristics
E
AS
I
AR
E
AR
Drain-to-Source Breakdown Voltage 500 ––– ––– V VGS = 0V, ID = 250µA
Static Drain-to-Source On-Resistance ––– ––– 0.45 Ω VGS = 10V, ID = 7.8A
Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 400V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 500V, VGS = 0V
µA
nA
VGS = -30V
Parameter Min. Typ. Max. Units Conditions
Forward Transconductance 7.5 ––– ––– S VDS = 50V, ID = 7.8A
Total Gate Charge ––– ––– 64 ID = 13A
Gate-to-Source Charge ––– ––– 17 nC VDS = 400V
Gate-to-Drain ("Miller") Charge ––– ––– 26 VGS = 10V, See Fig. 6 and 13
Turn-On Delay Time ––– 20 ––– VDD = 250V
Rise Time ––– 53 ––– ID = 13A
Turn-Off Delay Time ––– 43 ––– RG = 8.8Ω
ns
Fall Time ––– 42 ––– RD = 21Ω,See Fig. 10
Input Capacitance ––– 1900 ––– VGS = 0V
Output Capacitance ––– 290 ––– VDS = 25V
Reverse Transfer Capacitance ––– 12 ––– pF ƒ = 1.0MHz, See Fig. 5
Output Capacitance ––– 2615 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 76 ––– VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Parameter Typ. Max. Units
Single Pulse Avalanche Energy ––– 430 mJ
Avalanche Current ––– 13 A
Repetitive Avalanche Energy ––– 18 mJ
Thermal Resistance
Parameter Typ. Max. Units
R
Junction-to-Case ––– 0.70 °C/W
θJC
R
Junction-to-Ambient (PCB Mounted,steady-state) ––– 40
θJA
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
52
13
showing the
A
p-n junction diode.
G
Diode Forward Voltage ––– ––– 2.0 V TJ = 25°C, IS = 13A, VGS = 0V
Reverse Recovery Time ––– 540 810 ns TJ = 25°C, IF = 13A
Reverse RecoveryCharge ––– 4.1 6 . 1 µC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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D
S
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IRFBL12N50A
100
10
1
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
°
T = 25 C
0.1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
100
J
100
10
D
I , Drain-to-Source Current (A)
1
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20µs PULSE WIDTH
°
T = 150 C
J
1 10 100
V , Drain-to-Source Voltage (V)
DS
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
13A
2.5
°
T = 150 C
J
10
°
T = 25 C
J
1
D
I , Drain-to-Source Current (A)
V = 50V
DS
0.1
4.0 5.0 6.0 7.0 8.0
V , Gate-to-Source Voltage (V)
GS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
GS
°
10V
Vs. Temperature
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IRFBL12N50A
)
A
100000
10000
V
= 0V, f = 1 MHZ
GS
C
= C
iss
gs
C
= C
rss
gd
C
= C
ds
+ C
oss
+ Cgd, C
gd
Ciss
1000
Coss
100
C, Capacitance(pF)
10
1
1 10 100 1000
Crss
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
SHORTED
ds
20
I =
13A
D
V = 400V
DS
V = 250V
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
DS
V = 100V
DS
FOR TEST CIRCUIT
0
0 10 20 30 40 50 60
Q , Total Gate Charge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
T = 150°C
J
10
T = 25°C
SD
I , Reverse Drain Current (A)
1
0.4 0.6 0.8 1.0 1.2 1.4
V , Source-to-Drain Voltage (V
SD
J
V = 0V
Fig 7. Typical Source-Drain Diode
GS
100
10us
10
D
I , Drain Current (A)I , Drain Current (A)
1
°
= 25 C
C
T T= 150 C
Single Pulse
0.1
10 100 1000 10000
°
J
V , Drain-to-Source Voltage (V)
DS
100us
1ms
10ms
Fig 8. Maximum Safe Operating Area
Forward Voltage
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IRFBL12N50A
14
12
10
8
6
D
4
I , Drain Current (A)
2
0
25 50 75 100 125 150
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
1
R
V
DS
V
GS
R
G
D
D.U.T.
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
+
V
DD
-
D = 0.50
thJC
Thermal Response (Z )
0.001
0.20
0.1
0.10
0.05
0.02
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
t , Rectangular Pulse Duration (sec)
1
P
DM
1 2
J DM thJC C
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFBL12N50A
A
)
15V
DRIVER
+
-
V
R
20V
V
DS
G
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
Q
GD
DD
1000
TOP
800
600
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Junction Temperature ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
660
I
D
5.8A
8.2A
13A
°
V
G
640
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
Fig 13b. Gate Charge Test Circuit
620
600
DSav
V , Av alanche Voltage (V)
580
02468101214
I , A v ala n c he Cu rr e nt (A
av
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
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A
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IRFBL12N50A
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P.W.
+
-
VGS=10V
V
DD
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-Channel HEXFET® Power MOSFETs
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IRFBL12N50A
Super-D2PakTM Package Outline
Dimensions are shown in millimeters (inches)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Starting T
RG = 25Ω, I
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
= 25°C, L = 5.1mH
J
= 13A. (See Figure 12)
AS
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
Pulse width ≤ 300µs; duty cycle ≤ 2%.
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
Data and specifications subject to change without notice. 2/00
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