Page 1
SMPS MOSFET
Document Number: 91009
www.vishay.com
1
IRFBC30AS/LPbF
PD- 95534
HEXFET® Power MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptable Power Supply
l High speed power switching
l Lead-Free
V
DSS
Rds(on) max I
600V 2.2Ω 3.6A
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss specified (See AN 1001)
2
D Pak
TO-262
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 3.6
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 2.3 A
I
DM
PD @TC = 25°C Power Dissipation 74 W
V
GS
dv/dt Peak Diode Recovery dv/dt 7.0 V/ns
T
J
T
STG
Pulsed Drain Current 14
Linear Derating Factor 0.69 W/°C
Gate-to-Source Voltage ± 30 V
Operating Junction and -55 to + 150
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
D
Typical SMPS Topology:
l Single transistor Flyback
Notes through are on page 10
7/20/04
Page 2
IRFBC30AS/LPbF
Document Number: 91009
www.vishay.com
2
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 31 ––– VGS = 0V, VDS = 0V to 480V
oss
Avalanche Characteristics
E
AS
I
AR
E
AR
Drain-to-Source Breakdown Voltage 600 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.67 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance ––– ––– 2.2 Ω VGS = 10V, ID = 2.2A
Gate Threshold Voltage 2.0 ––– 4.5 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 480V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 100 V
Gate-to-Source Reverse Leakage ––– ––– -100
µA
nA
= 600V, VGS = 0V
V
DS
= 30V
GS
V
= -30V
GS
Parameter Min. Typ. Max. Units Conditions
Forward Transconductance 2.1 ––– ––– S VDS = 50V, ID = 2.2A
Total Gate Charge ––– ––– 23 ID = 3.6A
Gate-to-Source Charge ––– ––– 5.4 nC VDS = 480V
Gate-to-Drain ("Miller") Charge ––– ––– 11 VGS = 10V, See Fig. 6 and 13
Turn-On Delay Time ––– 9.8 ––– VDD = 300V
Rise Time ––– 13 ––– ID = 3.6A
Turn-Off Delay Time ––– 19 ––– RG = 12Ω
ns
Fall Time ––– 12 ––– RD = 82Ω,See Fig. 10
Input Capacitance ––– 510 ––– VGS = 0V
Output Capacitance ––– 70 ––– VDS = 25V
Reverse Transfer Capacitance ––– 3.5 ––– pF ƒ = 1.0MHz, See Fig. 5
Output Capacitance ––– 730 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 19 ––– VGS = 0V, VDS = 480V, ƒ = 1.0MHz
Parameter Typ. Max. Units
Single Pulse Avalanche Energy ––– 290 mJ
Avalanche Current ––– 3.6 A
Repetitive Avalanche Energy ––– 7.4 mJ
Thermal Resistance
R
θJC
R
θJA
Junction-to-Case ––– 1.7 °C/W
Junction-to-Ambient ( PCB Mounted, steady-state)* ––– 40
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
Diode Forward Voltage ––– ––– 1.6 V TJ = 25°C, IS = 3.6A, VGS = 0V
Reverse Recovery Time ––– 400 600 ns TJ = 25°C, IF = 3.6A
Reverse RecoveryCharge ––– 1.1 1.7 µC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Parameter Typ. Max. Units
––– –––
––– –––
3.6
14
showing the
A
p-n junction diode.
G
D
S
Page 3
IRFBC30AS/LPbF
Document Number: 91009
www.vishay.com
3
100
10
1
0.1
D
I , Drain-to-Source Current (A)
0.01
0.1 1 10 100
100
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
20µs PULSE WIDTH
T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
4.5V
°
10
1
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
°
T = 150 C
0.1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
3.6A
10
°
T = 150 C
J
1
°
T = 25 C
0.1
D
I , Drain-to-Source Current (A)
0.01
4.0 5.0 6.0 7.0 8.0 9.0
J
V = 50V
DS
20µs PULSE WIDTH
V , Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V =
GS
°
10V
Page 4
IRFBC30AS/LPbF
Document Number: 91009
www.vishay.com
4
10000
)
F
p
(
e
c
n
a
t
i
c
a
p
a
C
,
C
1000
100
10
V
= 0V, f = 1 MHZ
GS
C
= C
iss
gs
C
= C
rss
gd
C
= C
ds
+ C
oss
Ciss
Coss
+ Cgd, C
gd
Crss
1
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
SHORTED
ds
20
I =
3.6A
D
V = 480V
DS
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
V = 300V
DS
V = 120V
DS
FOR TEST CIRCUIT
0
0 4 8 12 16 20 24
Q , Total Gate Charge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
10
°
T = 150 C
J
°
T = 25 C
J
1
SD
I , Reverse Drain Current (A)
V = 0 V
0.1
0.4 0.6 0.8 1.0 1.2
V ,Source-to-Drain Voltage (V)
SD
GS
Fig 7. Typical Source-Drain Diode
Forward Voltage
10
1
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 150 C
Single Pulse
0.1
10 100 1000 10000
°
J
V , Drain-to-Source Voltage (V)
DS
10us
100us
1ms
10ms
Fig 8. Maximum Safe Operating Area
Page 5
4.0
Document Number: 91009
www.vishay.com
5
3.0
2.0
IRFBC30AS/LPbF
R
D.U.T.
D
+
V
DD
-
V
DS
V
GS
R
G
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
D
I , Drain Current (A)
1.0
Fig 10a. Switching Time Test Circuit
V
DS
90%
0.0
25 50 75 100 125 150
T , Case Temperature ( C)
C
°
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
10
thJC
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
Thermal Response (Z )
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRFBC30AS/LPbF
A
Document Number: 91009
www.vishay.com
6
15V
DRIVER
+
-
V
R
G
20V
V
DS
t
L
D.U.T
I
AS
Ω
0.01
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
Q
GD
DD
400
TOP
300
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Junction Temperature ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
740
I
D
1.6A
2.3A
3.6A
°
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
Fig 13b. Gate Charge Test Circuit
)
V
720
(
e
g
a
t
l
o
V
700
e
h
c
n
a
l
a
v
680
A
,
v
a
S
660
D
V
640
0.0 1.0 2.0 3.0 4.0
I
, Avalanche Current ( A)
AV
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Page 7
IRFBC30AS/LPbF
Document Number: 91009
www.vishay.com
7
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P. W .
+
+
V
DD
-
VGS=10V
*
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. ISDWaveform
Body Diode Forward
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
Fig 14. For N-Channel HEXFETS
Current
di/dt
Diode Recovery
dv/dt
V
DD
I
SD
Page 8
IRFBC30AS/LPbF
Document Number: 91009
www.vishay.com
8
2
D
Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F5 30S WIT H
LOT CODE 8024
ASS EMB L ED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
N ote: "P" in as s em bly line
po s i tion ind icate s "L ead-F ree"
INT E R NAT ION AL
RECTIFIER
LOGO
AS SE MB LY
LOT CODE
OR
IN T ER NAT ION AL
RECTIFIER
LOGO
AS S EM B LY
LOT CODE
F 530S
PART NUMB ER
DATE CODE
P = DESIGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 0 = 2000
WEEK 02
A = ASSEMBLY SITE CODE
F530S
PART NUMBER
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
Page 9
TO-262 Package Outline
Document Number: 91009
www.vishay.com
9
IRFBC30AS/LPbF
TO-262 Part Marking Information
EXAMPLE:
TH IS IS AN IRL 3103L
LOT CODE 1789
ASS EMB LE D ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
Note: "P" in as sembly line
pos ition i ndicates "L ead-F ree"
OR
INT ER NAT IONAL
RE CTIF IER
LOGO
ASSEMBLY
LOT CODE
INT ER NAT IONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
DATE CODE
YE AR 7 = 1997
WEEK 19
LINE C
PART NUMBE R
DATE CODE
P = D E S IGN AT E S L E AD- F R E E
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WE E K 19
A = ASSEMBLY SITE CODE
Page 10
IRFBC30AS/LPbF
Document Number: 91009
www.vishay.com
10
D2Pak Tape & Reel Infomation
TRR
FEED DIRECTION
TRL
FEED DIRECTION
1.85 (.073)
1.65 (.065)
10.90 (.42 9)
10.70 (.42 1)
4.10 (.161)
3.90 (.153)
1.60 (.063)
1.50 (.059)
11.60 (.457 )
11.40 (.449 )
16.10 (.634)
15.90 (.626)
1.60 (.0 63)
1.50 (.0 59)
1.75 (.069)
1.25 (.049)
15.42 (.6 09)
15.22 (.6 01)
0.368 (. 0145)
0.342 (. 0135)
24.30 (. 957)
23.90 (. 941)
4.72 (.136)
4.52 (.178)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
27.40 (1.079)
23.90 (.941)
4
26.40 (1.039)
24.40 (.961)
3
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
4
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
C
eff. is a fixed capacitance that gives the same charging time
Starting T
RG = 25Ω, I
I
SD
= 25°C, L = 46mH
J
AS
≤ 3.6A, di/dt ≤ 170A/µs, V
TJ ≤ 150°C
= 3.6A. (See Figure 12)
≤ V
DD
(BR)DSS
,
oss
as C
oss
while V
is rising from 0 to 80% V
DS
Uses IRFBC30A data and test condi-
tions
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
DSS
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
07/04
Page 11
Legal Disclaimer Notice
Vishay
Notice
The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of
International Rectifier’s Power Control Systems (PCS) business, which closed in April 2007. Specifications of the
products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below.
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or
anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
International Rectifier
are registered trademarks of International Rectifier Corporation in the U.S. and other countries. All other product
names noted herein may be trademarks of their respective owners.
®
, IR®, the IR logo, HEXFET®, HEXSense®, HEXDIP®, DOL®, INTERO®, and POWIRTRAIN
®
Document Number: 99901 www.vishay.com
Revision: 12-Mar-07 1
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