Page 1
PD - 97772
Single Pulse Avalanche Energy
Repetitive Avalanche Energy
IRFB4510PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
Absolute Maximum Ratings
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
I
@ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
D
I
DM
PD @TC = 25°C
V
GS
dv/dt
T
J
T
STG
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
c
e
D
S
D
S
D
G
TO-220AB
IRFB4510PbF
GDS
100V
10.7m
13.5m
62A
Ω
Ω
Gate Drain Source
Max.
62
44
250
140
0.95
± 20
3.2
-55 to + 175
300
10lb
x
in (1.1Nx m)
A
W
W/°C
V
V/ns
°C
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Thermal Resistance
R
θ
JC
R
θ
CS
R
θ
JA
www.irf.com 1
d
f
Junction-to-Case
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient, TO-220
i
i
130
See Fig. 14, 15, 22a, 22b,
–––
0.50 ––– °C/W
––– 62
1.05
mJ
A
mJ
4/10/12
Page 2
IRFB4510PbF
= 25°C (unless otherwise specified)
Drain-to-Source Breakdown Voltage
/ΔTJ Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
100nAGate-to-Source Reverse Leakage
RGInternal Gate Resistance
–––5887nCQgsGate-to-Source Charge
QgdGate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
Reverse Transfer Capacitance
ISContinuous Source Current
1.3VtrrReverse Recovery Time
QrrReverse Recovery Charge
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
J
(BR)DSS
(BR)DSS
DS(on)
GS(th)
DSS
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
sync
d(on)
d(of f)
iss
oss
rss
oss
oss
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
g
g
Diode Characteristics
VGS = 0V, ID = 250μA
Reference to 25°C, I
VGS = 10V, ID = 37A
= 5mA
D
f
VDS = VGS, ID = 100μA
V
= 100V, VGS = 0V
DS
= 80V, VGS = 0V, TJ = 125°C
V
DS
= 20V
V
GS
= -20V
V
GS
VDS = 25V, ID = 37A
= 37A
I
D
V
=50V
DS
VGS = 10V
I
= 37A, VDS =0V, VGS = 10V
D
f
VDD = 65V
I
= 37A
D
R
=2.7
G
VGS = 10V
f
VGS = 0V
= 50V
V
DS
ƒ = 1.0MHz, See Fig.5
= 0V, VDS = 0V to 80V
V
GS
VGS = 0V, VDS = 0V to 80V
c
f
h
g
(Body Diode)
(Body Diode)
RRM
Notes:
c
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
RG = 25Ω , I
above this value.
I
≤ 37A, di/dt ≤ 1550A/μs, V
SD
, starting TJ = 25°C, L = 0.192mH
Jmax
= 37A, VGS =10V. Part not recommended for use
AS
DD
≤ V
(BR)DSS
, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 37A, VGS = 0V
C
eff. (TR) is a fixed capacitance that gives the same charging time
oss
as C
C
C
R
while V
oss
eff. (ER) is a fixed capacitance that gives the same energy as
oss
while V
oss
is measured at TJ approximately 90°C.
θ
is rising from 0 to 80% V
DS
is rising from 0 to 80% V
DS
DSS
DSS
.
.
D
G
S
f
2 www.irf.com
Page 3
IRFB4510PbF
1000
)
A
(
t
n
100
e
r
r
u
C
e
c
r
u
10
o
S
o
t
n
i
a
r
1
D
,
D
I
0.1
0.1 1 10 100
4.0V
≤
Tj = 25°C
TOP 15V
10V
4.3V
BOTTOM 4.0V
60μ s PULSE WIDTH
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
)
Α
(
t
n
100
e
r
r
u
C
e
c
r
u
10
o
S
o
t
n
i
a
r
D
1
,
D
I
0.1
2.0 3.0 4.0 5.0 6.0 7.0
TJ = 175°C
TJ = 25°C
V
= 50V
DS
60μ s PULSE WIDTH
≤
VGS, Gate-to-Source Voltage (V)
VGS
6.0V
5.0V
4.8V
4.5V
1000
)
A
(
t
n
e
r
r
u
C
e
c
r
u
o
S
o
t
n
i
a
r
D
,
I
TOP 15V
10V
100
4.3V
BOTTOM 4.0V
10
D
1
0.1 1 10 100
VGS
6.0V
5.0V
4.8V
4.5V
4.0V
60μ s PULSE WIDTH
≤
Tj = 175°C
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
3.0
e
c
n
a
t
s
i
s
e
R
n
O
e
c
r
u
o
S
o
t
n
i
a
r
D
,
)
n
o
(
S
D
R
ID = 37A
V
= 10V
GS
2.5
2.0
)
d
e
z
i
l
1.5
a
m
r
o
N
(
1.0
0.5
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
100000
10000
)
F
p
(
e
c
n
a
t
i
1000
c
a
p
a
C
,
C
100
10
1 10 100
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
+ Cgd, C
gs
gd
+ C
ds
ds
gd
C
C
iss
rss
oss
Ciss
Coss
Crss
VDS, Drain-to-Source Voltage (V)
SHORTED
Fig 4. Normalized On-Resistance vs. Temperature
14
ID= 37A
)
12
V
(
e
g
a
t
10
l
o
V
e
c
8
r
u
o
S
-
6
o
t
e
t
a
4
G
,
S
G
V
2
0
0 2 04 06 08 0
VDS= 80V
VDS= 50V
VDS= 20V
Q
Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
www.irf.com 3
Page 4
IRFB4510PbF
1000
)
A
(
t
100
n
e
r
r
u
C
n
i
a
r
10
D
e
s
r
e
v
e
R
,
1
D
S
I
0.1
TJ = 175°C
TJ = 25°C
V
= 0V
GS
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
70
60
)
50
A
(
t
n
e
r
40
r
u
C
n
i
30
a
r
D
,
D
20
I
10
0
25 50 75 100 125 150 175
TJ, Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
1000
)
A
(
t
n
100
e
r
r
u
C
e
c
r
u
10
o
S
o
t
n
i
a
r
D
1
,
D
I
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
11 01 0 0
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100μ sec
1msec
10msec
DC
VDS, Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
)
V
(
125
e
g
a
t
l
o
V
n
w
o
d
k
a
e
r
B
e
c
r
u
o
S
o
t
n
i
a
r
D
,
S
S
D
)
R
B
(
V
Id = 5mA
120
115
110
105
100
95
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
1.2
1.0
0.8
)
J
μ
(
y
0.6
g
r
e
n
E
0.4
0.2
0.0
0 20 40 60 80 100
V
Drain-to-Source Voltage (V)
DS,
600
)
J
m
(
y
500
g
r
e
n
E
e
400
h
c
n
a
l
a
v
300
A
e
s
l
u
P
200
e
l
g
n
i
S
,
100
S
A
E
0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
TOP 4.7A
BOTTOM37A
I
D
12A
Fig 11. Typical C
Stored Energy
OSS
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4 www.irf.com
Page 5
IRFB4510PbF
10
W
/
C
°
1
)
C
J
h
t
Z
(
e
s
n
o
p
s
e
R
l
a
m
r
e
h
T
0.001
100
)
A
(
t
n
e
r
r
u
C
e
h
c
n
a
l
a
v
A
0.1
0.01
10
1
D = 0.50
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Duty Cycle = Single Pulse
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
140
TOP Single Pulse
120
)
J
m
(
y
100
g
r
e
n
E
80
e
h
c
n
a
60
l
a
v
A
,
40
R
A
E
20
0
25 50 75 100 125 150 175
BOTTOM 1% Duty Cycle
ID = 37A
Starting TJ , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
tav (sec)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
2. Safe operation in Avalanche is allowed as long asT
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
. This is validated for every part type.
jmax
is not exceeded.
jmax
= Average power dissipation per single avalanche pulse.
during avalanche).
6. I
= Allowable avalanche current.
av
7. ΔT = Allowable rise in junction temperature, not to exceed T
(assumed as
jmax
25°C in Figure 14, 15).
t
Average time in avalanche.
av =
D = Duty cycle in avalanche = t
Z
(D, tav) = Transient thermal resistance, see Figures 13)
thJC
P
D (ave)
·f
av
= 1/2 ( 1.3·BV·Iav) = D T/ Z
I
2D T/ [1.3·BV·Zth]
av =
E
= P
AS (AR)
D (ave)·tav
thJC
www.irf.com 5
Page 6
IRFB4510PbF
4.5
)
V
4.0
(
e
g
a
t
l
3.5
o
V
d
l
o
3.0
h
s
e
r
h
t
2.5
e
t
a
G
,
)
h
t
(
S
G
V
2.0
1.5
ID = 100μA
ID = 250μA
ID = 1.0mA
ID = 1.0A
1.0
-75 -50 -25 0 25 50 75 100 125 150 175 200
TJ , Temperature ( °C )
Fig 16. Threshold Voltage vs. Temperature
24
20
24
20
16
)
A
(
-
12
M
R
R
I
8
4
0
100 200 300 400 500 600 700 800 900 1000
IF = 24A
VR = 80V
TJ = 125°C
TJ = 25°C
dif / dt - (A / μs)
Fig. 17 - Typical Recovery Current vs. di f/dt
600
500
16
)
A
(
-
12
M
R
R
I
8
4
0
100 200 300 400 500 600 700 800 900 1000
IF = 37A
VR = 80V
TJ = 125°C
TJ = 25°C
dif / dt - (A / μs)
)
C
n
(
R
R
Q
600
500
400
)
C
n
(
-
300
R
R
Q
200
100
0
100 200 300 400 500 600 700 800 900 1000
IF = 37A
VR = 80V
TJ = 125°C
TJ = 25°C
dif / dt - (A / μs)
400
300
200
100
0
100 200 300 400 500 600 700 800 900 1000
IF = 24A
VR = 80V
TJ = 125°C
TJ = 25°C
dif / dt - (A / μs)
Fig. 19 - Typical Stored Charge vs. di f/dt Fig. 18 - Typical Recovery Current vs. di f/dt
Fig. 20 - Typical Stored Charge vs. di f/dt
6 www.irf.com
Page 7
IRFB4510PbF
Reverse
Recovery
Current
Driver Gate Drive
D.U.T. ISDWaveform
D.U.T. VDSWaveform
Inductor Current
Inductor Curent
* V
GS
D.U.T
+
-
R
G
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-
• dv/dt controlled by R
• Driver same type as D.U.T.
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
+
V
DD
Re-Applied
Voltage
+
-
Period
P.W.
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P. W .
Period
VGS=10V
V
DD
I
SD
*
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
t
15V
V
DS
L
DRIVER
p
R
G
20V
Fig 22a. Unclamped Inductive Test Circuit
Second Pulse Width < 1μs
D.U.T
I
AS
Ω
0.01
t
p
V
DS
V
GS
Duty Factor < 0.1%
L
D.U.T
+
V
DD
-
I
AS
Fig 22b. Unclamped Inductive Waveforms
D
V
DS
+
-
V
DD
90%
10%
V
GS
t
t
d(on)
r
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Id
Vgs
L
VCC
0
20K
1K
DUT
t
d(off)
t
f
Vds
Vgs(th)
Qgs1
Qgs2 Qgd Qgodr
Fig 24a. Gate Charge Test Circuit
www.irf.com 7
Fig 24b. Gate Charge Waveform
Page 8
IRFB4510PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
AS S EMBL E D ON WW 19, 2000
IN T HE ASSEMBLY LINE "C"
Note: "P" in assembly line pos ition
i ndi cates "L ead - F ree"
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
INTERNATIONAL
RECT IFIER
LOGO
ASSEMBLY
LOT CODE
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
Visit us at www.irf.com for sales contact information. 04/12
8 www.irf.com
PART NUMBER
DATE CODE
YE AR 0 = 2000
WE E K 19
LINE C
TAC Fax: (310) 252-7903