Datasheet IRFB 4310Z Datasheet

)

PD - 97115C

IRFB4310ZPbF IRFS4310ZPbF

IRFSL4310ZPbF

HEXFET® Power MOSFET

Applications

l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

G

D

V

DSS

R

DS(on

max. I

D

(Silicon Limited)

I

D

S

(Package Limited)

D

typ.

SOA

l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free

S

D

G

TO-220AB

IRFB4310ZPbF

GDS

IRFS4310ZPbF

Gate Drain Source

G

D2Pak

S

D

IRFSL4310ZPbF

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

I

@ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

D

I

@ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited

D

I

DM

@TC = 25°C

P

D

V

GS

dv/dt T

J

T

STG

Pulsed Drain Current

Maximum Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Peak Diode Recovery

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Mounting torque, 6-32 or M3 screw

d

f

Max.

c

127

c

90

120

560

250

1.7

± 20

18

-55 to + 175

300

10lbxin (1.1Nxm)

4.8m

6.0m

127A

D

TO-262

100V

: :

120A

G

A

W

W/°C

V

V/ns

°C

c

D

S

Avalanche Characteristics

g

e

130

See Fig. 14, 15, 22a, 22b,

mJ

E

AS (Thermally limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

c

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

R

JA

θ

Junction-to-Case

Case-to-Sink, Flat Greased Surface , TO-220

Junction-to-Ambient, TO-220

Junction-to-Ambient (PCB Mount) , D2Pak

k –––

0.50 ––– °C/W

k ––– 62

jk

––– 40

0.6

www.irf.com 1

A

9/18/09

IRFB/S/SL4310ZPbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

ΔV

(BR)DSS

R

DS(on)

V

GS(th)

I

DSS

I

GSS

R

G

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 150 ––– ––– S

Q

g

Q

gs

Q

gd

Q

sync

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

eff. (ER)

C

oss

eff. (TR)

C

oss

Drain-to-Source Breakdown Voltage 100 ––– ––– V

/ΔT

Breakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 4.8 6.0

Gate Threshold Voltage 2.0 ––– 4.0 V

Drain-to-Source Leakage Current ––– ––– 20 μA

––– ––– 250

Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

Internal Gate Resistance ––– 0.7 ––– Ω

Total Gate Charge ––– 120 170 nC

Gate-to-Source Charge ––– 29 –––

Gate-to-Drain ("Miller") Charge ––– 35

Total Gate Charge Sync. (Qg - Qgd)

––– 85 –––

Turn-On Delay Time ––– 20 ––– ns

Rise Time ––– 60 –––

Turn-Off Delay Time ––– 55 –––

Fall Time ––– 57 –––

Input Capacitance ––– 6860 ––– pF

Output Capacitance ––– 490 –––

Reverse Transfer Capacitance ––– 220 –––

Effective Output Capacitance (Energy Related)

Effective Output Capacitance (Time Related)h

––– 570 –––

––– 920 –––

VGS = 0V, ID = 250μA

Reference to 25°C, I

= 10V, ID = 75A g

V

mΩ

GS

= VGS, ID = 150μA

V

DS

= 100V, VGS = 0V

V

DS

= 80V, VGS = 0V, TJ = 125°C

V

DS

VGS = 20V

= -20V

V

GS

VDS = 50V, ID = 75A

= 75A

I

D

=50V

V

DS

V

= 10V g

GS

I

= 75A, VDS =0V, VGS = 10V

D

V

= 65V

DD

= 75A

I

D

= 2.7Ω

R

G

VGS = 10V g

= 0V

V

GS

= 50V

V

DS

ƒ = 1.0MHz, See Fig. 5

= 0V, VDS = 0V to 80V i, See Fig. 11

V

GS

= 0V, VDS = 0V to 80V h

V

GS

Conditions

= 5mAd

D

Conditions

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

I

RRM

t

on

Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 120A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements.

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 25Ω, I above the Eas value and test conditions.

 I

≤ 75A, di/dt ≤ 600A/μs, V

SD

Continuous Source Current ––– –––

127c

(Body Diode) Pulsed Source Current ––– ––– 560 A

(Body Diode)d Diode Forward Voltage ––– ––– 1.3 V

Reverse Recovery Time ––– 40 ns

––– 49

Reverse Recovery Charge ––– 58 nC

––– 89

Reverse Recovery Current ––– 2.5 ––– A

Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

 Pulse width ≤ 400μs; duty cycle ≤ 2%.  C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

as C

 C

C

while V

oss

eff. (ER) is a fixed capacitance that gives the same energy as

oss

while V

oss

DS

is rising from 0 to 80% V

DS

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

, starting TJ = 25°C, L = 0.047mH

Jmax

= 75A, VGS =10V. Part not recommended for use

AS

DD

≤ V

(BR)DSS

, TJ ≤ 175°C.

mended footprint and soldering techniques refer to application note #AN-994.

 R

is measured at TJ approximately 90°C

θ

A

MOSFET symbol

showing the integral reverse

p-n junction diode.

= 25°C, IS = 75A, VGS = 0V g

T

J

TJ = 25°C VR = 85V,

= 125°C IF = 75A

T

J

TJ = 25°C

= 125°C

T

J

TJ = 25°C

is rising from 0 to 80% V

Conditions

di/dt = 100A/μs g

.

DSS

.

DSS

G

2 www.irf.com

D

S

IRFB/S/SL4310ZPbF

1000

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

TOP 15V

100

BOTTOM 4.5V

10

VGS

10V

8.0V

6.0V

5.5V

5.0V

4.8V

4.5V

≤

60μs PULSE WIDTH

Tj = 25°C

1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

)

Α

(

t n

100

e

r

r u

C e

c

r u

10

o S

o

t

n

i a

r

1

D ,

D

I

0.1

TJ = 175°C

TJ = 25°C

V

= 50V

DS

≤

60μs PULSE WIDTH

2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, Gate-to-Source Voltage (V)

1000

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

TOP 15V

BOTTOM 4.5V

100

VGS

10V

8.0V

6.0V

5.5V

5.0V

4.8V

4.5V

≤

60μs PULSE WIDTH

Tj = 175°C

10

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

2.5

e c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D

,

) n o

( S D

R

ID = 75A

V

= 10V

GS

2.0

) d e z

i

l a

1.5

m

r o

N

(

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

) F p

( e

c n a

t

i c a p a

C ,

C

12000

10000

8000

6000

4000

2000

0

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

+ Cgd, C

gs

gd

+ C

ds

gd

C

iss

rss

oss

Ciss

Coss

Crss

VDS, Drain-to-Source Voltage (V)

SHORTED

Fig 4. Normalized On-Resistance vs. Temperature

20

ID= 75A

) V

(

16

e g a

t

l o V

e

12

c

r u o S

o

t

8

e

t a

G ,

S

4

G

V

0

0 40 80 120 160 200

VDS= 80V

VDS= 50V VDS= 20V

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

www.irf.com 3

IRFB/S/SL4310ZPbF

1000

10000

OPERATION IN THIS AREA

) A

( t

100

n e

r

r u

C n

i a

r

10

D e

s

r e v e

R ,

D S

I

0.1

TJ = 175°C

TJ = 25°C

1

V

= 0V

GS

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

) A

(

1000

t n e

r

r u

C

100

e c

r u o S

o

t

10

n

i a

r D

,

1

D

I

Tc = 25°C Tj = 175°C Single Pulse

0.1

0.1 1 10 100

VSD, Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

LIMITED BY RDS(on)

1msec

100μsec

10msec

DC

VDS, Drain-toSource Voltage (V)

Forward Voltage

e g

140

LIMITED BY PACKAGE

120

) A

100

( t n e

r

80

u C n

i a

60

r D

,

D

40

I

20

0

25 50 75 100 125 150 175

TC, Case Temperature (°C)

Fig 9. Maximum Drain Current vs.

130

a

t

l o V

n w

o d k a e

r B

e c

r u o S

o

t

n

i a

r D

,

V

ID = 5mA

120

110

100

S S D

) R B

(

90

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 10. Drain-to-Source Breakdown Voltage

Case Temperature

3.0

2.5

2.0

) J

μ

( y

1.5

g

r e n E

1.0

0.5

0.0

0 20 40 60 80 100

V

Drain-to-Source Voltage (V)

DS,

600

) J

m

( y

500

g

r e n E

e

400

h c n a

l a v

300

A e

s

l u P

200

e

l g n

i S

100

, S A

E

0

25 50 75 100 125 150 175

I

TOP

11A

19A

BOTTOM

Starting TJ, Junction Temperature (°C)

D

75A

Fig 11. Typical C

Stored Energy

OSS

Fig 12. Maximum Avalanche Energy Vs. DrainCurrent

4 www.irf.com

IRFB/S/SL4310ZPbF

τ

1

0.1

0.01

D = 0.50

0.20

0.10

0.05

0.02

0.01

SINGLE PULSE ( THERMAL RESPONSE )

τ

J

τ

J

τ

1

τ

1

Ci= τi/Ri

R

1

2

R

1

τ

3

R

2

3

τ

2

3

τ

2

3

Ri (°C/W)

4

R

4

0.018756 0.000007

τ

C

0.159425 0.000117

τ

4

τ

4

0.320725 0.001817

0.101282 0.011735

Notes:

1. Duty Factor D = t1/t2

)

C J h

t Z (

e s n o p s e

R l a

m

r e h T

2. Peak Tj = P dm x Zthjc + Tc

0.001

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100

Duty Cycle = Single Pulse

) A

(

10

t n e

r

r u

C e

h c n a

l a

1

v A

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤj = 25°C and

0.01

0.05

0.10

Tstart = 150°C.

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

τι

(sec)

0.1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

140

TOP Single Pulse

120

) J

m

(

100

y g

r e n E

80

e h c n a

60

l a v A ,

40

R A

E

20

0

25 50 75 100 125 150 175

BOTTOM 1% Duty Cycle ID = 75A

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T

2. Safe operation in Avalanche is allowed as long asT

. This is validated for every part type.

jmax

is not exceeded.

jmax

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P

= Average power dissipation per single avalanche pulse.

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ΔT = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14). t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see Figures 13)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 15. Maximum Avalanche Energy vs. Temperature

www.irf.com 5

IRFB/S/SL4310ZPbF

4.5

) V

4.0

( e

g a

t

l

3.5

o V

d

l o

3.0

h s e

r h

t

2.5

e

t a

G )

2.0

h

t

(

S G

1.5

V

1.0

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 1.0A

ID = 1.0mA

ID = 250μA

ID = 150μA

TJ , Temperature ( °C )

Fig 16. Threshold Voltage Vs. Temperature

24

20

24

20

16

) A

(

-

12

M R R

I

8

4

0

100 200 300 400 500 600 700 800 900 1000

IF = 30A

VR = 85V

TJ = 125°C

TJ = 25°C

dif / dt - (A / μs)

Fig. 17 - Typical Recovery Current vs. dif/dt

600

500

16

) A

(

-

12

M R R

I

8

4

0

100 200 300 400 500 600 700 800 900 1000

IF = 45A

VR = 85V

TJ = 125°C

TJ = 25°C

dif / dt - (A / μs)

400

) C

n

(

-

300

R R

Q

200

100

600

500

400

) C

n

(

-

300

R R

Q

200

100

0

100 200 300 400 500 600 700 800 900 1000

IF = 45A

VR = 85V

TJ = 125°C

TJ = 25°C

dif / dt - (A / μs)

IF = 30A

VR = 85V

TJ = 125°C

TJ = 25°C

0

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

Fig. 20 - Typical Stored Charge vs. dif/dt

6 www.irf.com

IRFB/S/SL4310ZPbF

A





D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

*

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

**

* Use P-Channel Driver for P-Channel Measurements ** Reverse Polarity for P-Channel

Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs

15V

V

DS

L

DRIVER

DD

+

-

Reverse Recovery Current

Re-Applied Voltage

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

*** V

Period

P.W.

Body Diode Forward

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

GS

Current

di/dt

Diode Recovery

dv/dt

t

p

D =

P. W .

Period

V

(BR)DSS

***

VGS=10V

V

DD

I

SD

R

V

20V

G

GS

D.U.T

I

AS

0.01

t

p

Ω

Fig 22a. Unclamped Inductive Test Circuit

R

V

DS

V

GS

R

G

D

D.U.T.

10V

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

Fig 23a. Switching Time Test Circuit

0

20K

1K

DUT

+

V

DD

-

I

AS

Fig 22b. Unclamped Inductive Waveforms

V

DS

90%

+

V

DD

-

10%

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig 23b. Switching Time Waveforms

Id

Vgs

Vds

L

VCC

Vgs(th)

Qgs1

Qgs2QgdQgodr

Fig 24a. Gate Charge Test Circuit

www.irf.com 7

Fig 24b. Gate Charge Waveform

IRFB/S/SL4310ZPbF

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

EXAMPLE: T HIS IS AN IRF1010

LOT CODE 1789 ASS EMBL E D ON WW 19, 2000 IN THE ASSEMBLY LINE "C"

Note: "P" in assembly line position

indi cates "L ead - F r ee"

TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

INTE RNAT IONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

8 www.irf.com

PART NUMBER

DAT E CODE YEAR 0 = 2000 WEEK 19 LINE C

TO-262 Package Outline (Dimensions are shown in millimeters (inches))

IRFB/S/SL4310ZPbF

TO-262 Part Marking Information

EXAMPLE : THIS IS AN IRL3103L

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

www.irf.com 9

LOT CODE 1789 ASS EMBL E D ON WW 19, 1997 IN THE ASS EMBLY LINE "C"

OR

INTERNATIONAL

INTERNAT IONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

RECTIFIER

LOGO

ASSEMBLY LOT CODE

PART NUMBER

DATE CODE YEAR 7 = 1997 WEEK 19 LINE C

PART NUMBER

DAT E CODE P = D E S IGN AT E S L EAD -F RE E

PRODUCT (OPTIONAL) YEAR 7 = 1997 WE E K 1 9 A = AS S E MBL Y S I T E CODE

IRFB/S/SL4310ZPbF

D2Pak Package Outline (Dimensions are shown in millimeters (inches))

D2Pak Part Marking Information

THIS IS AN IRF530S WITH

LOT CODE 8024 AS S E MBLE D ON WW 02, 2000 IN T HE AS SEMBLY LINE "L"

T HIS IS AN IRF 530S WIT H

LOT CODE 8024 AS S E MBLE D ON WW 02, 2000 IN T HE ASSEMBLY LINE "L"

INTE RNATIONAL

RECTIF IER

LOGO

ASSEMBLY LOT CODE

INTE RNATIONAL

RECTIF IER

LOGO

LOT CODE

F530S

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

10 www.irf.com

PART NUMBER

DATE CODE YEAR 0 = 2000 WEEK 02 LINE L

PART NUMBER

DATE CODE

D2Pak Tape & Reel Information

TRR

4.10 (.161)

3.90 (.153)

1.60 (.063)

1.50 (.059)

1.60 (.063)

1.50 (.059)

IRFB/S/SL4310ZPbF

0.368 (.0145)

0.342 (.0135)

FEED DIRECTION

TRL

FEED DIRECTION

330.00 (14.173) MAX.

1.85 (.073)

1.65 (.065)

10.90 (.429)

10.70 (.421)

13.50 (.532)

12.80 (.504)

11.60 (.457)

11.40 (.449)

1.75 (.069)

1.25 (.049)

16.10 (.634)

15.90 (.626)

15.42 (.609)

15.22 (.601)

27.40 (1.079)

23.90 (.941)

4

24.30 (.957)

23.90 (.941)

4.72 (.136)

4.52 (.178)

60.00 (2.362) MIN.

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

26.40 (1.039)

24.40 (.961)

3

30.40 (1.197) MAX.

4

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 9/08

www.irf.com 11