Datasheet IRFB4115PbF Datasheet

PD - 97354

)

IRFB4115PbF

HEXFET® Power MOSFET

Applications

l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

SOA

l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free

D

V

DSS

R

DS(on

G

GDS

max. I

D

S

typ.

(Silicon Limited)

S

D

G

TO-220AB

150V

9.3m 11m

104A

Ω

Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V

@ TC = 100°C Continuous Drain Current, VGS @ 10V

I

D

I

DM

@TC = 25°C

P

D

V

GS

dv/dt Peak Diode Recovery T

J

T

STG

Pulsed Drain Current

Maximum Power Dissipation W

Linear Derating Factor W/°C

Gate-to-Source Voltage V

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Mounting torque, 6-32 or M3 screw

c

e

Max.

104

74

420

380

2.5

± 20

18

-55 to + 175

300

10lbxin (1.1Nxm)

Avalanche Characteristics

E

AS (Thermally limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

c

f

d

See Fig. 14, 15, 22a, 22b

220

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

Junction-to-Case

Case-to-Sink, Flat Greased Surface 0.50 ––– °C/W

Junction-to-Ambient

j

ij

––– 0.40

––– 62

A

V/ns

°C

mJ

A

mJ

www.irf.com 1

11/10/08

IRFB4115PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

∆V

(BR)DSS

R

DS(on)

V

GS(th)

I

DSS

I

GSS

R

G

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 97 ––– ––– S Q

g

Q

gs

Q

gd

Q

sync

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

C

eff. (ER)

oss

C

eff. (TR)

oss

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

I

RRM

t

on

Drain-to-Source Breakdown Voltage 150 ––– ––– V

/∆T

Breakdown Voltage Temp. Coefficient ––– 0.18 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 9.3 11

mΩ Gate Threshold Voltage 3.0 ––– 5.0 V Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250 Gate-to-Source Forward Leakage ––– ––– 100 nA Gate-to-Source Reverse Leakage ––– ––– -100 Internal Gate Resistance ––– 2.3 –––

Total Gate Charge ––– 77 120 nC Gate-to-Source Charge ––– 28 ––– Gate-to-Drain ("Miller") Charge ––– 26 ––– Total Gate Charge Sync. (Qg - Qgd)

––– 51 ––– Turn-On Delay Time ––– 18 ––– ns Rise Time ––– 73 ––– Turn-Off Delay Time ––– 41 ––– Fall Time ––– 39 ––– Input Capacitance ––– 5270 ––– pF Output Capacitance ––– 490 ––– Reverse Transfer Capacitance ––– 105 ––– Effective Output Capacitance (Energy Related) ––– 460 ––– Effective Output Capacitance (Time Related) ––– 530 –––

Continuous Source Current ––– ––– 104 A (Body Diode) Pulsed Source Current ––– ––– 420 A (Body Diode)

d

Diode Forward Voltage ––– ––– 1.3 V Reverse Recovery Time ––– 86 ––– ns

––– 110 ––– Reverse Recovery Charge ––– 300 ––– nC

––– 450 ––– Reverse Recovery Current ––– 6.5 ––– A Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

VGS = 0V, ID = 250µA Reference to 25°C, I

= 10V, ID = 62A

V

GS

V

= VGS, ID = 250µA

DS

V

= 150V, VGS = 0V

DS

V

= 150V, VGS = 0V, TJ = 125°C

DS

V

= 20V

GS

= -20V

V

GS

Ω

VDS = 50V, ID = 62A I

= 62A

D

= 75V

V

DS

f

= 10V

V

GS

= 62A, VDS =0V, VGS = 10V

I

D

V

= 98V

DD

I

= 62A

D

= 2.2Ω

R

G

VGS = 10V V

GS

V

DS

f

= 0V = 50V

ƒ = 1.0 MHz, See Fig. 5 V

= 0V, VDS = 0V to 120V h, See Fig. 11

GS

V

= 0V, VDS = 0V to 120V

GS

MOSFET symbol showing the integral reverse p-n junction diode.

= 25°C, IS = 62A, VGS = 0V

T

J

T

= 25°C VR = 130V,

J

T

= 125°C IF = 62A

J

T

= 25°C

J

T

= 125°C

J

T

= 25°C

J

Conditions

= 3.5mA

D

f

Conditions

di/dt = 100A/µs

c

g

D

G

S

f

Notes:

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 25Ω, I above this value.

 I

≤ 62A, di/dt ≤ 1040A/µs, V

SD

, starting TJ = 25°C, L = 0.11mH

Jmax

= 62A, VGS =10V. Part not recommended for use

AS

DD

≤ V

(BR)DSS

, TJ ≤ 175°C.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

 C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

as C

 C

C

while V

oss

eff. (ER) is a fixed capacitance that gives the same energy as

oss

while V

oss

is rising from 0 to 80% V

DS

is rising from 0 to 80% V

DS

DSS

.

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 R

is measured at TJ approximately 90°C.

θ

2 www.irf.com

IRFB4115PbF

1000

5.0V

VGS

10V

8.0V

7.0V

6.5V

6.0V

5.5V

60µs PULSE WIDTH

≤

Tj = 25°C

TOP 15V

) A

(

100

t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

BOTTOM 5.0V

10

1

0.1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

) A

(

t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

D

100

10

TJ = 175°C

1

TJ = 25°C

V

= 50V

DS

≤

60µs PULSE WIDTH

0.1 2 4 6 8 10 12 14 16

VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

1000

VGS

10V

8.0V

7.0V

6.5V

6.0V

5.5V

5.0V

60µs PULSE WIDTH

≤

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

100

10

D

TOP 15V

BOTTOM 5.0V

Tj = 175°C

1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

3.0

e c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D

,

) n o

( S D

R

) d e z

i

l a

m

r o

N

(

2.5

2.0

1.5

1.0

ID = 62A

V

= 10V

GS

0.5

-60 -40 -20 0 20 40 60 80 100120140 160180

TJ , Junction Temperature (°C)

Fig 4. Normalized On-Resistance vs. Temperature

100000

10000

) F p

( e

c n a

t

1000

i c a p a

C ,

C

100

V

= 0V, f = 1 MHZ

GS

C

= C

C

iss

rss

oss

C

= C

C

rss

iss

oss

+ Cgd, C

gs

gd

+ C

ds

SHORTED

ds

gd

10

1 10 100 1000

VDS, Drain-to-Source Voltage (V)

14.0 ID= 62A

12.0

) V

( e

g

10.0

a

t

l o V

e

8.0

c

r u o S

-

6.0

o

t

e

t a

4.0

G ,

S G

V

2.0

VDS= 120V

VDS= 75V

VDS= 30V

0.0 0 20406080100

QG, Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

www.irf.com 3

IRFB4115PbF

1000

) A

( t n e

r

r u

C n

i a

r D e

s

r e v e

R ,

D S

I

TJ = 175°C

100

10

TJ = 25°C

1

0.1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VSD, Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode

Forward Voltage

120

100

) A

(

80

t n e

r

r u

C

60

n

i a

r D

40

,

D

I

20

0

25 50 75 100 125 150 175

TC , Case Temperature (°C)

Fig 9. Maximum Drain Current vs.

V

GS

= 0V

10000

) A

( t

1000

n e

r

r u

C e

c

r u

100

o S

o

t

n

i a

r D

10

,

D

I

DC

Tc = 25°C Tj = 175°C Single Pulse

1

1 10 100 1000

OPERATION IN THIS AREA LIMITED BY RDS(on)

100µsec

1msec

10msec

VDS, Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

) V

(

200

e g a

t

l o V

n w

o d k a e

r B

e c

r u o S

o

t

n

i a

r D

,

S S D

) R B

(

V

Id = 3.5mA

190

180

170

160

150

140

-60 -40 -20 0 20 40 60 80 100120140 160180

TJ , Temperature ( °C )

Fig 10. Drain-to-Source Breakdown Voltage

Case Temperature

6.0

5.0

4.0

) J µ

( y

3.0

g

r e n E

2.0

1.0

0.0

-20 0 20 40 60 80 100 120 140 160

V

Drain-to-Source Voltage (V)

DS,

Fig 11. Typical C

Stored Energy

OSS

900

) J

m

800

( y

g

r

700

e n E

e

600

h c n a

l

500

a v

A

400

e s

l u P

300

e

l g n

i

200

S ,

S

100

A

E

0

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

TOP 10A

BOTTOM 62A

I

D

22A

Fig 12. Maximum Avalanche Energy vs. DrainCurrent

4 www.irf.com

IRFB4115PbF

τ

1

W

/ C

° )

C J h

t

Z (

e

0.01

s n o p s e

R l a

0.001

m

r e h T

0.1

D = 0.50

0.20

0.10

0.05

0.02

0.01

τ

J

τ

J

τ

1

τ

Ci= τi/Ri

R

1

2

R

1

2

τ

1

2

τ

2

SINGLE PULSE ( THERMAL RESPONSE ) Notes:

R

3

Ri (°C/W) τi (sec)

R

3

τ

C

τ

3

0.0500 0.000052

0.1461 0.000468

τ

3

0.2041 0.004702

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche

100

) A

( t n e

r

r u

C e

h c n a

l a v A

10

0.01

0.05

0.10

1

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τj = 25°C and

Tstart = 150°C.

0.1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

pulsewidth, tav, assuming ∆Tj = 150°C and Tstart =25°C (Single Pulse)

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

250

TOP Single Pulse BOTTOM 1.0% Duty Cycle

)

200

J m

( y

g

r e n

150

E e

h c n a

l

100

a v

A ,

R A

50

E

ID = 62A

0

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T

2. Safe operation in Avalanche is allowed as long asT

. This is validated for every part type.

jmax

is not exceeded.

jmax

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P

= Average power dissipation per single avalanche pulse.

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ∆T = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14, 15). t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see Figures 13)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 15. Maximum Avalanche Energy vs. Temperature

www.irf.com 5

IRFB4115PbF

6.0

) V

(

5.0

e g a

t

l o V

d

l

4.0

o h s e

r h

t e

t a

G ,

) h

t

( S G

V

ID = 250µA

ID = 1.0mA

3.0 ID = 1.0A

2.0

1.0

-75 -50 -25 0 25 50 75 100 125 150 175

TJ , Temperature ( °C )

Fig 16. Threshold Voltage vs. Temperature

50

IF = 62A

VR = 130V

40

TJ = 25°C

TJ = 125°C

30

) A

(

R R

I

20

50

IF = 42A

VR = 130V

40

TJ = 25°C

TJ = 125°C

30

) A

(

R R

I

20

10

0

0 200 400 600 800 1000

diF /dt (A/µs)

Fig. 17 - Typical Recovery Current vs. dif/dt

2500

IF = 42A

VR = 130V

TJ = 25°C

TJ = 125°C

) A

(

Q

R R

2000

1500

1000

10

0

0 200 400 600 800 1000

diF /dt (A/µs)

3000

2400

1800

) A

(

R R

Q

1200

600

0

500

0

0 200 400 600 800 1000

diF /dt (A/µs)

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

IF = 62A

VR = 130V

TJ = 25°C

TJ = 125°C

0 200 400 600 800 1000

diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

6 www.irf.com

IRFB4115PbF

A

+

-

+

-





Reverse Recovery Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Current

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied Voltage

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

V

15V

V

DS

L

DRIVER

t

p

(BR)DSS

R

G

V

20V

GS

D.U.T

I

AS

0.01

t

p

Ω

+

V

DD

-

Fig 22a. Unclamped Inductive Test Circuit

R

V

DS

V

GS

R

G

10V

V

GS

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

D

D.U.T.

Fig 23a. Switching Time Test Circuit

Current Regulator

Same Type as D.U.T.

50KΩ

.2µF

12V

V

GS

.3µF

D.U.T.

3mA

I

Current Sampling Resistors

I

G

+

V

DS

-

D

I

AS

Fig 22b. Unclamped Inductive Waveforms

V

DS

90%

V

DD

10% V

GS

t

d(on)tr

t

d(off)tf

Fig 23b. Switching Time Waveforms

Vds

Vgs(th)

Qgs1

Qgs2 Qgd Qgodr

Id

Vgs

Fig 24a. Gate Charge Test Circuit

www.irf.com 7

Fig 24b. Gate Charge Waveform

IRFB4115PbF

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

(;$03/( 7+,6,6$1,5)

/27&2'( $66(0%/('21:: ,17+($66(0%/</,1(&

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LQGLFDWHV/HDG)UHH

TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

,17(51$7,21$/

5(&7,),(5

/2*2

$66(0%/< /27&2'(

http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

Visit us at www.irf.com for sales contact information. 11/2008

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3$57180%(5

'$7(&2'( <($5  :((. /,1(&

TAC Fax: (310) 252-7903