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SMPS MOSFET
PD- 93805B
IRFB31N20D
IRFS31N20D
IRFSL31N20D
HEXFET® Power MOSFET
Applications
l High frequency DC-DC converters
V
DSS
R
DS(on)
max I
200V 0.082Ω 31A
Benefits
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective C
App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
to Simplify Design, (See
OSS
TO-220AB
IRFB31N20D
D2Pak
IRFS31N20D
TO-262
IRFSL31N20D
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 31
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 21 A
I
DM
PD @TA = 25°C Power Dissipation 3.1 W
PD @TC = 25°C Power Dissipation 200
V
GS
dv/dt Peak Diode Recovery dv/dt 2.1 V/ns
T
J
T
STG
Pulsed Drain Current 124
Linear Derating Factor 1.3 W/°C
Gate-to-Source Voltage ± 30 V
Operating Junction and -55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)
D
°C
Typical SMPS Topologies
l Telecom 48V Input Forward Converters
Notes through are on page 11
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2/14/00
Page 2
IRFB/IRFS/IRFSL31N20D
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 170 ––– VGS = 0V, VDS = 0V to 160V
oss
Avalanche Characteristics
E
AS
I
AR
E
AR
Thermal Resistance
R
θJC
R
θCS
R
θJA
R
θJA
Diode Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
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Drain-to-Source Breakdown Voltage 200 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient
J
––– 0.25 ––– V/°C Reference to 25°C, ID = 1mA
Static Drain-to-Source On-Resistance ––– ––– 0.082 Ω VGS = 10V, ID = 18A
Gate Threshold Voltage 3.0 ––– 5.5 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 160V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 200V, VGS = 0V
µA
nA
VGS = -30V
Parameter Min. Typ. Max. Units Conditions
Forward Transconductance 17 ––– ––– S VDS = 50V, ID = 18A
Total Gate Charge ––– 70 110 ID = 18A
Gate-to-Source Charge ––– 18 27 nC VDS = 160V
Gate-to-Drain ("Miller") Charge ––– 33 49 VGS = 10V,
Turn-On Delay Time ––– 16 ––– VDD = 100V
Rise Time ––– 38 ––– ID = 18A
Turn-Off Delay Time ––– 26 ––– RG = 2.5Ω
ns
Fall Time ––– 10 ––– RD = 5.4Ω
Input Capacitance ––– 2370 – –– VGS = 0V
Output Capacitance ––– 390 ––– VDS = 25V
Reverse Transfer Capacitance ––– 78 ––– pF ƒ = 1.0MHz
Output Capacitance ––– 2860 – –– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 150 ––– VGS = 0V, VDS = 160V, ƒ = 1.0MHz
Parameter Typ. Max. Units
Single Pulse Avalanche Energy ––– 420 mJ
Avalanche Current ––– 18 A
Repetitive Avalanche Energy ––– 20 mJ
Parameter Typ. Max. Units
Junction-to-Case ––– 0.75
Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
Junction-to-Ambient ––– 62
Junction-to-Ambient ––– 40
Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 18A, VGS = 0V
Reverse Recovery Time ––– 200 300 ns TJ = 25°C, IF = 18A
Reverse RecoveryCharge ––– 1.7 2.6 µC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
31
124
showing the
A
p-n junction diode.
G
D
S
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IRFB/IRFS/IRFSL31N20D
1000
100
10
1
D
I , Drain-to-Source Current (A)
0.1
0.1 1 10 100
1000
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.5V
6.0V
BOTTOM
5.5V
20µs PULSE WIDTH
5.5V
T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
°
1000
100
10
TOP
BOTTOM
VGS
15V
12V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.5V
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
T = 175 C
°
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
30A
2.5
100
°
T = 175 C
J
10
°
T = 25 C
J
1
D
I , Drain-to-Source Current (A)
V = 50V
DS
0.1
5 6 7 8 9 10 11
V , Gate-to-Source Voltage (V)
GS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
GS
°
10V
Vs. Temperature
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IRFB/IRFS/IRFSL31N20D
100000
10000
V
= 0V, f = 1 MHZ
GS
C
= C
iss
gs
C
= C
rss
gd
C
= C
ds
+ C
oss
+ Cgd, C
gd
Ciss
1000
Coss
C, Capacitance(pF)
100
Crss
10
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
SHORTED
ds
20
I =
18A
D
V = 160V
DS
V = 100V
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
DS
V = 40V
DS
FOR TEST CIRCUIT
0
0 20 40 60 80 100
Q , Total Gate Charge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
100
°
T = 175 C
J
10
°
T = 25 C
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.4 0.6 0.8 1.0 1.2
V ,Source-to-Drain Voltage (V)
SD
J
V = 0 V
GS
Fig 7. Typical Source-Drain Diode
100
10
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 175 C
Single Pulse
1
1 10 100 1000
°
J
V , Drain-to-Source Voltage (V)
DS
Fig 8. Maximum Safe Operating Area
10us
100us
1ms
10ms
Forward Voltage
4 www.irf.com
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IRFB/IRFS/IRFSL31N20D
R
D.U.T.
D
+
V
DD
-
30
25
20
V
DS
V
GS
R
G
10V
15
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
10
D
I , Drain Current (A)
5
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
thJC
0.20
0.1
0.10
P
1 2
DM
t
1
t
2
0.05
Thermal Response (Z )
0.01
0.02
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 6
IRFB/IRFS/IRFSL31N20D
A
15V
DRIVER
+
-
V
R
V
G
20V
DS
L
D.U.T
I
AS
0.01
t
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
DD
1000
TOP
800
600
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting T , Junction Temperature ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
D
7.3A
15A
18A
°
Current Regulator
Q
G
10 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
Same Type as D.U.T.
.2µF
12V
V
GS
50KΩ
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
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Page 7
IRFB/IRFS/IRFSL31N20D
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P.W.
+
-
VGS=10V
V
DD
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-channel HEXFET® Power MOSFETs
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Page 8
IRFB/IRFS/IRFSL31N20D
A
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
2.87 (.113)
2.62 (.103)
15.24 (.60 0)
14.84 (.58 4)
14.09 (.5 55)
13.47 (.5 30)
1.40 (.05 5)
3X
1.15 (.04 5)
2.54 (.10 0)
NOTES:
1 DIMEN S IONING & TO LE RAN C ING P E R AN S I Y14.5M, 1982. 3 OUTL INE C ON F O R M S TO JE D E C OU T LINE TO -220A B .
2 C O N T RO L L ING D IME NSIO N : IN CH 4 H E AT S IN K & L EAD M E A SU R E ME N TS DO N OT INCLUDE BURRS.
2X
10.29 (.405)
4
1 2 3
3X
0.36 ( .0 1 4 ) M B A M
6.47 (.255)
6.10 (.240)
1.15 (.04 5)
MIN
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
3.78 (.149)
3.54 (.139)
- A -
4.69 (.18 5)
4.20 (.16 5)
- B -
1.32 (.05 2)
1.22 (.04 8)
2.92 (.115)
2.64 (.104)
LEAD ASSIGNMENTS
1 - G ATE
2 - D RA IN
3 - S OU RC E
4 - D RA IN
0.55 (.02 2)
3X
0.46 (.01 8)
TO-220AB Part Marking Information
EXAM PLE : THIS IS AN IRF1010
W IT H A SS EMBL Y
LOT CODE 9 B1 M
INTERNATIONAL
RECTIFIER
LOG O
ASSEMBLY
LO T CODE
IRF1010
9246
9B 1M
PART NUMBER
DATE CODE
(YYWW)
YY = YEAR
W W = W EEK
8 www.irf.com
Page 9
D2Pak Package Outline
A
IRFB/IRFS/IRFSL31N20D
10.54 (.415)
1.40 (.055)
MAX.
1.78 (.070)
1.27 (.050)
1.40 (.055)
3X
1.14 (.045)
5.08 (.200)
NOTE S:
1 DIMENSIONS AFTER SOLDER DIP.
2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
3 CONTROLLING DIM ENSION : INCH.
4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS.
2
D
Pak Part Marking Information
10.29 (.405)
- A 2
1 3
15.49 (.610)
14.73 (.580)
0.93 (.037)
3X
0.69 (.027)
0.2 5 ( .0 10 ) M B A M
4.69 (.185)
4.20 (.165)
5.28 (.208)
4.78 (.188)
0.55 (.022)
0.46 (.018)
- B -
1.32 (.052)
1.22 (.048)
2.79 (.110)
2.29 (.090)
1.39 (.055)
1.14 (.045)
LEAD ASSIGNMENTS
1 - G ATE
2 - D RA IN
3 - S OURCE
10.16 (.400)
REF .
6.47 (.255)
6.18 (.243)
2.61 (.103)
2.32 (.091)
8.89 (.350)
REF .
MINIMUM RECOMMENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
17.78 (.700)
3.81 (.150)
2.08 (.082)
2X
2.54 (.100)
2X
INTERNATIONAL
RE CTIFIER
L O G O
A S SEMBLY
LO T CO D E
F530S
9246
9 B 1M
PART NUM B ER
DATE CODE
(YYW W )
YY = YEAR
WW = WEEK
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Page 10
IRFB/IRFS/IRFSL31N20D
TO-262 Package Outline
TO-262 Par t Mar king Information
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Page 11
D2Pak Tape & Reel Information
TRR
FEED DIRECTION
TRL
FEED DIRECTION
1.85 (.073)
1.65 (.065)
10.90 (.429)
10.70 (.421)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
IRFB/IRFS/IRFSL31N20D
1.60 (.063)
11.60 (.457)
11.40 (.449)
16.10 (.634)
15.90 (.626)
1.50 (.059)
1.75 (.069)
1.25 (.049)
15.42 (.609 )
15.22 (.601 )
0.368 (.0145)
0.342 (.0135)
24.30 (.957)
23.90 (.941)
4.72 (.136)
4.52 (.178)
27.40 (1.079)
23.90 (.941)
4
26.40 (1.0 39 )
24.40 (.961)
3
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
4
330.00
(14.173)
MA X.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
Notes:
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Repetitive rating; pulse width limited by
13.50 (.532)
12.80 (.504)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature.
Starting T
RG = 25Ω, I
I
SD
= 25°C, L = 3.8mH
J
= 18A.
AS
≤ 18A, di/dt ≤ 110A/µs, V
DD
≤ V
(BR)DSS
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
,
This is only applied to TO-220AB package
oss
while V
is rising from 0 to 80% V
DS
DSS
TJ ≤ 175°C
This is applied to D
2
Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
Data and specifications subject to change without notice. 2/2000
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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