Datasheet IRF9530NSPBF Specification

Page 1
PD - 91523A
IRF9530NS/L
HEXFET® Power MOSFET
l Advanced Process Technology l Surface Mount (IRF9530NS) l Low-profile through-hole (IRF9530NL) l 175°C Operating Temperature l Fast Switching l P-Channel l Fully Avalanche Rated
G
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.
2
Pak is a surface mount power package capable of
The D accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on­resistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF9530NL) is available for low­profile applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -14 ID @ TC = 100°C Continuous Drain Current, VGS @ -10V -10 A I
DM
PD @TA = 25°C Power Dissipation 3.8 W PD @TC = 25°C Power Dissipation 79 W
V
GS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt  -5.0 V/ns T
J
T
STG
Pulsed Drain Current  -56
Linear Derating Factor 0.53 W/°C Gate-to-Source Voltage ± 20 V Single Pulse Avalanche Energy 250 mJ Avalanche Current -8.4 A Repetitive Avalanche Energy 7.9 mJ
Operating Junction and -55 to + 175 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
Junction-to-Case ––– 1.9 Junction-to-Ambient ( PCB Mounted,steady-state)** –– – 40
2
D Pak
D
V
R
DS(on)
= -100V
DSS
= 0.20Ω
ID = -14A
S
TO-262
°C/W
°C
5/13/98
Page 2
IRF9530NS/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Drain-to-Source Breakdown Voltage -100 ––– ––– V VGS = 0V, ID = -250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– -0.11 ––– V/°C Reference to 25°C, ID = -1mA
J
Static Drain-to-Source On-Resistance ––– ––– 0.20 Ω VGS = -10V, ID = -8.4A Gate Threshold Voltage -2.0 ––– -4.0 V VDS = VGS, ID = -250µA Forward Transconductance 3.2 ––– ––– S VDS = -50V, ID = -8.4A
Drain-to-Source Leakage Current
––– ––– -25
––– ––– -250 VDS = -80V, VGS = 0V, TJ = 150°C Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V Gate-to-Source Reverse Leakage ––– ––– -100
VDS = -100V, VGS = 0V
µA
nA
VGS = -20V Total Gate Charge ––– ––– 58 ID = -8.4A Gate-to-Source Charge ––– ––– 8.3 nC VDS = -80V Gate-to-Drain ("Miller") Charge ––– ––– 32 VGS = -10V, See Fig. 6 and 13  Turn-On Delay Time ––– 15 ––– VDD = -50V Rise Time ––– 58 ––– ID = -8.4A Turn-Off Delay Time ––– 45 ––– RG = 9.1Ω
ns
Fall Time ––– 46 ––– RD = 6.2Ω, See Fig. 10
Internal Source Inductance
––– –––
7.5
Between lead,
nH
and center of die contact Input Capacitance ––– 760 ––– VGS = 0V Output Capacitance ––– 260 ––– pF VDS = -25V Reverse Transfer Capacitance ––– 170 ––– ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting T
RG = 25Ω, I
I
SD
TJ ≤ 175°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode) 
––– –––
––– –––
-14
-56
showing the
A
p-n junction diode. Diode Forward Voltage ––– ––– -1.6 V TJ = 25°C, IS = -8.4A, VGS = 0V Reverse Recovery Time ––– 130 190 ns TJ = 25°C, IF = -8.4A Reverse Recovery Charge ––– 650 970 nC di/dt = -100A/µs Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
= 25°C, L =7.0mH
J
= -8.4A. (See Figure 12)
AS
≤ -8.4A, di/dt ≤ -490A/µs, V
DD
≤ V
(BR)DSS
Uses IRF9530N data and test conditions
,

D
G
S
Page 3
IRF9530NS/L
A
A
)
A
100
VGS TOP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V BOTTOM - 4.5V
10
1
D
-I , Drain-to -S ou rce C urre nt (A )
-4.5V
20µs PULSE WIDTH
TJ = 25°C TJ = 175°C
T = 25 °C
0.1
0.1 1 10 1 00
-V , Drain-to-S ource Voltage (V)
DS
100
c
100
VGS TOP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V BOTTOM - 4.5V
10
-4.5V
1
D
-I , Drain-to-Source Current (A)
20µs PULSE WIDTH T = 175°C
0.1
0.1 1 10 100
-V , Dra in-t o- S o u rc e Voltage (V
DS
C
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
2.5
I =
D
-14A
T = 25°C
10
1
D
-I , D rain- to-S o urc e C u rre nt (A )
0.1 45678910
J
T = 175°C
J
V = -50 V
DS
20µs PULSE W IDTH
-V , Ga te-to-Source Volta ge (V)
GS
Fig 3. Typical Transfer Characteristics
2.0
1.5
1.0
(Normalized)
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperature( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V =
GS
°
-10V
Page 4
IRF9530NS/L
A
)
A
2000
1600
1200
800
C, Capacitance (pF)
400
0
1 10 100
V = 0V, f = 1M Hz
GS
C = C + C , C S H O RTE D
iss gs gd ds
C = C
rss g d
C = C + C
oss ds g d
C
iss
C
oss
C
rss
-V , Drai n-to - S o ur c e Voltage (V
DS
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
20
I =
-8.4A
D
15
10
5
V =-80V
DS
V =-50V
DS
V =-20V
DS
GS
-V , Gate-to-Source Voltage (V)
FOR TEST CIRCUIT
0
0 10 20 30 40 50 60
Q , Total Gate Charge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
T = 150°C
J
T = 25°C
J
1
V = 0 V
0.4 0.6 0.8 1.0 1.2 1.4 1.6
-V , So urce- to -D r ain V o lta g e (V)
SD
-I , Reverse Drain Current (A)
10
SD
0.1
Fig 7. Typical Source-Drain Diode
Forward Voltage
GS
100
10us
100us
10
D
-I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 175 C Single Pulse
1
1 10 100 1000
°
J
-V , Drain-to-Source Voltage (V)
DS
1ms
10ms
Fig 8. Maximum Safe Operating Area
Page 5
IRF9530NS/L
14
12
10
8
6
D
4
-I , Drain Current (A)
2
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
R
D.U.T.
D
-
+
V
DS
V
GS
R
G
-10V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
GS
10%
90% V
DS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
V
DD
thJC
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
Therm al Response (Z )
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SIN G L E P U L S E (THERMAL RESP ONSE)
Note s:
1. Du ty fac tor D = t / t
2. Pea k T = P x Z + T
t , R ectangular Pulse Duration (sec)
1
J
DM
P
12
thJC
DM
t
1
t
2
C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
A
Page 6
IRF9530NS/L
(BR)
L
D.U.T
I
AS
0.01
t
p
DRIVER
Ω
15V
V
DD
R
-20V
V
DS
G
Fig 12a. Unclamped Inductive Test Circuit
I
AS
t
p
V
DSS
700
600
TOP BOTTOM
A
500
400
300
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting T , Junction Temperature ( C)
J
I
D
-3.4A
-5.9A
-8.4A
°
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Q
G
-10V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T .
-3mA
I
G
Current Sampling Resistors
­V
DS
+
I
D
Fig 13b. Gate Charge Test Circuit
Page 7
IRF9530NS/L
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
-
R
G
V
GS
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance Current Transformer
-
-
• dv/dt controlled by R
• ISD controlled by Duty Factor "D"
+
G
• D.U.T. - Device Under Test
P.W.
D =
Period
+
V
DD
-
VGS=10V
[ ] ***
Reverse Recovery Current
Re-Applied Voltage
D.U.T. ISDWaveform
Body Diode Forward
Current
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
*** V
= 5.0V for Logic Level and 3V Drive Devices
GS
di/dt
Diode Recovery
dv/dt
Fig 14. For P-Channel HEXFETS
V
DD
[ ]
I
[ ]
SD
Page 8
IRF9530NS/L
A
D2Pak Package Outline
10.54 (.415)
1.40 (.055) MAX.
1.78 (.070)
1.27 (.050)
1.40 (.055)
3X
1.14 (.045)
5.08 (.200)
NOTE S: 1 DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS.
10.29 (.405)
- A ­2
1 3
15.49 (.610)
14.73 (.580)
0.93 (.037)
3X
0.69 (.027)
0.2 5 ( .0 10) M B A M
Part Marking Information
D2Pak
4.69 (.185)
4.20 (.165)
5.28 (.208)
4.78 (.188)
0.55 (.022)
0.46 (.018)
- B -
1.32 (.052)
1.22 (.048)
2.79 (.110)
2.29 (.090)
1.39 (.055)
1.14 (.045)
LEAD ASSIGNMENTS 1 - G ATE 2 - D RAIN 3 - S OU R CE
10.16 (.400) REF.
6.47 (.255)
6.18 (.243)
2.61 (.103)
2.32 (.091)
8.89 (.350) REF.
MINIMUM RECOMMENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
17.78 (.700)
3.81 (.150)
2.08 (.082) 2X
2.54 (.100) 2X
INTERNATIONAL RE CTIFIE R LO G O
A S SEMBLY LO T CO D E
F530S
9246
9 B 1 M
PART NUM B ER
DATE CODE (YYW W ) YY = YEAR WW = WEEK
Page 9
Package Outline
TO-262 Outline
IRF9530NS/L
Part Marking Information
TO-262
Page 10
IRF9530NS/L
Tape & Reel Information
D2Pak
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
1.60 (.063)
1.50 (.059)
0.368 (.0145)
0.342 (.0135)
FEED D IRECTION
1.85 (.073)
1.65 (.065)
TRL
10.90 (.429)
10.70 (.421)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
330.00 (14.173) MAX.
NOTES :
1. COM FO R M S TO E IA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
11.60 (.457)
11.40 (.449)
1.75 (.069)
1.25 (.049)
16.10 (.634)
15.90 (.626)
15.42 (.609)
15.22 (.601)
27.40 (1.079)
23.90 (.941)
4
26.4 0 (1.039)
24.40 (.961 )
3
24.30 (.957)
23.90 (.941)
4.72 (.136)
4.52 (.178)
60.00 (2.362) MIN.
30.40 (1.197) MAX .
4
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
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http://www.irf.com/ Data and specifications subject to change without notice. 5/98
Page 11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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