This advanced power MOSFET is designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. These are
P-Channel enhancement mode silicon gate power field
effecttransistors designed for applications such as switching
regulators, switching converters, motor drivers, relay drivers
and drivers for high power bipolar switching transistors
requiring high speed and low gate drive power. These types
can be operated directly from integrated circuits.
Formerly developmental type TA17501.
Ordering Information
PART NUMBERPACKAGEBRAND
IRF9520TO-220ABIRF9520
NOTE: When ordering, use the entire part number.
File Number
Features
• 6A, 100V
DS(ON)
= 0.600Ω
•r
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
Symbol
D
G
S
2281.3
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
4-3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
370mJ
-55 to 150
300
260
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to TJ = 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
Zero Gate Voltage Drain CurrentI
DSSID
GS(TH)VGS
DSS
= -250µA, VGS = 0V (Figure 10)-100--V
= VDS, ID = -250µA-2--4V
VDS = Rated BV
VDS = 0.8 x Rated BV
, VGS = 0V---25µA
DSS
DSS
, VGS = 0V
---250µA
TC = 125oC
On-State Drain Current (Note 2)I
D(ON)
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 2)r
DS(ON)ID
Forward Transconductance (Note 2)g
Turn-On Delay Timet
d(ON)
Rise Timet
Turn-Off Delay Timet
d(OFF)
Fall Timet
Total Gate Charge
Q
g(TOT)VGS
(Gate to Source + Gate to Drain)
Gate to Source ChargeQ
Gate to Drain “Miller” ChargeQ
Input CapacitanceC
Output CapacitanceC
Reverse Transfer CapacitanceC
Internal Drain InductanceL
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
1.6
1.2
VGS = -10V
0.8
, DRAIN TO SOURCE
ON RESISTANCE (Ω)
DS(ON)
0.4
r
0
0-5-10-15-20-25
I
, DRAIN CURRENT (A)
D
VGS = -20V
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.2
V
= -10V, ID = -4A
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
1.8
1.4
1.0
ON RESISTANCE
0.6
NORMALIZED DRAIN TO SOURCE
0.2
-40040
, JUNCTION TEMPERATURE (oC)
T
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4-6
80
120
Page 5
IRF9520
Typical Performance Curves
1.25
ID = 250µA
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-40040
T
, JUNCTION TEMPERATURE (oC)
J
Unless Otherwise Specified (Continued)
80120160
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
3
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
500
400
300
200
C, CAPACITANCE (pF)
100
0
0
C
ISS
C
OSS
C
RSS
V
-10
DS
-20
, DRAIN TO SOURCE VOLTAGE (V)
VGS= 0V, f = 1MHz
C
= CGS + C
ISS
C
= C
RSS
C
≈ CDS+ C
OSS
-30-40
GD
GD
GD
-50
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-100
2
TJ = -55oC
T
= 25oC
1
, TRANSCONDUCTANCE (S)
fs
g
0
0-2-4-6-8-10
ID, DRAIN CURRENT (A)
J
= 125oC
T
J
-10
-1.0
, DRAIN CURRENT (A)
SD
I
-0.1
-0.4
TJ = 150oC
V
SD
TJ = 25oC
-0.8-1.4
-1.0-1.2-1.6-1.8-0.6
, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
0
-5
, GATE TO SOURCE (V)
-10
GS
V
VDS = -50V
V
= -20V
DS
ID = -6A
VDS = -80V
4-7
0481216
Q
, TOTAL GATE CHARGE (nC)
g(TOT)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
20
Page 6
IRF9520
Test Circuits and Waveforms
V
DS
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V
V
GS
t
P
AS
L
R
G
-
V
DD
+
DUT
I
AS
0.01Ω
0
V
DD
I
AS
t
P
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
BV
t
AV
DSS
V
DS
t
ON
t
d(ON)
t
R
L
DUT
R
V
GS
G
-
V
DD
+
0
V
DS
V
GS
0
10%
r
10%
90%
50%
PULSE WIDTH
FIGURE 17. SWITCHING TIME TEST CIRCUITFIGURE 18. RESISTIVE SWITCHING WAVEFORMS
-V
DS
D
(ISOLATED
SUPPLY)
DUT
0
V
DS
Q
gs
Q
gd
12V
BATTERY
0.2µF
50kΩ
CURRENT
REGULATOR
0.3µF
t
d(OFF)
90%
V
GS
t
OFF
50%
90%
t
f
10%
Q
g(TOT)
S
CURRENT
I
D
SAMPLING
DUT
+V
DS
V
DD
0
I
G(REF)
G
0
I
G(REF)
IG CURRENT
SAMPLING
RESISTORRESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUITFIGURE 20. GATE CHARGE WAVEFORMS
4-8
Page 7
IRF9520
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
4-9
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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