Datasheet irf830.rev0 Datasheet

Page 1

IRF830

Power Field Effect Transistor

N–Channel Enhancement Mode Silicon Gate TMOS

This TMOS Power FET is designed for high voltage, high speed power switching applications such as switching regulators, converters, solenoid and relay drivers.

• Silicon Gate for Fast Switching Speeds

• Low R

Temperature

• Rugged — SOA is Power Dissipation Limited

• Source–to–Drain Diode Characterized for Use with Inductive Loads

MAXIMUM RATINGS

Drain–Source Voltage V Drain–Gate Voltage (RGS = 1.0 MΩ) V Gate–Source Voltage V Drain Current

Continuous, T

Peak, T

Total Power Dissipation @ TC = 25°C

Derate above 25°C

Operating and Storage

T emperature Range

THERMAL CHARACTERISTICS

Thermal Resistance

— Junction–to–Case — Junction–to–Ambient

Maximum Lead Temperature for

Soldering Purposes, 1/8″ from Case for 5 Seconds

to Minimize On–Losses, Specified at Elevated

DS(on)

Rating Symbol Value Unit

DSS DGR

TJ, T

R R

stg

JA L

–55 to 150 °C

= 25°C

= 100°C

500 Vdc 500 Vdc

20 Vdc

4.5

3.0 18

0.6

1.67

62.5 300 °C

Adc

Watts

W/°C

°C/W

http://onsemi.com

TMOS POWER FET

4.5 AMPERES 500 VOLTS

DS(on)



= 1.5 Ω

TO–220AB

CASE 221A

STYLE 5

N–Channel

See the MTM4N45 Data Sheet for a complete set of design curves for the product on this data sheet. Design curves of the MTP4N45 are applicable for this product.

 Semiconductor Components Industries, LLC, 2000

April, 2000 – Rev. 0

1 Publication Order Number:

PIN ASSIGNMENT

1 2 3 Source 4

Gate

Drain

ORDERING INFORMATION

Device Package Shipping

IRF830 TO–220AB 50 Units/Rail

IRF830/D

Page 2

IRF830

)

f 1.0 MHz)

(

DD D

)

Vdc, I

Rated ID)

)

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Characteristic

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

= 0 Vdc, ID = 0.25 mAdc)

Zero Gate Voltage Drain Current

= Rated V

= 0.8 Rated V

, VGS = 0 Vdc)

DSS

, VGS = 0 Vdc, TJ = 125°C)

DSS

Gate–Body Leakage Current, Forward

= 20 Vdc, VDS = 0)

GSF

Gate–Body Leakage Current, Reverse

= 20 Vdc, VDS = 0)

GSR

ON CHARACTERISTICS

(1)

Gate Threshold Voltage

= VGS, ID = 0.25 mA)

Static Drain–to–Source On–Resistance

= 10 Vdc, ID = 2.5 Adc)

On–State Drain Current (VGS = 10 V)

≥ 6.75 Vdc)

Forward Transconductance

≥ 6.75 Vdc, ID = 2.5 Adc)

DYNAMIC CHARACTERISTICS

Input Capacitance Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS

(1)

Turn–On Delay Time t Rise Time Turn–Off Delay Time

= 200 Vdc, ID = 2.5 Apk,

RG = 15 Ω)

Fall Time t Total Gate Charge Gate–Source Charge

(VDS = 0.8 Rated V

= 10 Vdc, I

= Rated I

DSS

Gate–Drain Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

(1)

Forward On–Voltage Forward Turn–On Time

(IS = Rated ID,

= 0

Reverse Recovery Time

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

Symbol Min Max Unit

(BR)DSS

Vdc

500 —

DSS

GSS(f)

— —

0.2

1.0

mAdc

nAdc

— 100

GSS(r)

nAdc

— 100

GS(th)

Vdc

2.0 4.0

DS(on)

Ohm

— 1.5

D(on)

Adc

4.5 —

mhos

2.5 —

C C C

d(on)

d(off)

Q Q Q

iss oss rss

gs gd

SD on

— 800 pF — 200 — 60

— 30 ns — 30 — 55

— 30 22 (Typ) 30 nC 12 (Typ) — 10 (Typ) —

1.1 (Typ) 1.6 Vdc Limited by stray inductance

450 (Typ) — ns

3.5 (Typ)

4.5 (Typ)

— —

7.5 (Typ) —

http://onsemi.com

Page 3

IRF830

P ACKAGE DIMENSIONS

TO–220AB

CASE 221A–09

ISSUE Z

SEATING

–T–

PLANE

123

R J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73

G 0.095 0.105 2.42 2.66

H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33

Q 0.100 0.120 2.54 3.04

R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 V 0.045 ––– 1.15 ––– Z ––– 0.080 ––– 2.04

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

http://onsemi.com

Page 4

IRF830

E–FET is a trademark of Semiconductor Components Industries, LLC. TMOS is a registered trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected]

Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich T ime)

Email: ONlit–[email protected]

French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse T ime)

Email: ONlit–[email protected]

English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)

Email: [email protected]