Datasheet IRF8113 Datasheet (IRF)

Applications

A

l Synchronous MOSFET for Notebook

Processor Power

l Synchronous Rectifier MOSFET for

Isolated DC-DC Converters in Networking Systems

Benefits

l Very Low R l Low Gate Charge l Fully Characterized Avalanche Voltage

DS(on)

at 4.5V V

GS

and Current

l 100% Tested for R

G

V

DSS

30V

S

5.6m:@V

1

2

3

4

Top View

PD - 94637B

IRF8113

HEXFET® Power MOSFET

R

8

7

6

5

DS(on)

A

D

DG

max

= 10V

GS

Qg Typ.

24nC

SO-8

Absolute Maximum Ratings

V

DS

V

GS

@ TA = 25°C

I

D

@ TA = 70°C

I

D

I

DM

PD @TA = 25°C

@TA = 70°C

P

D

T

J

T

STG

Parameter Units

Drain-to-Source Voltage V

Gate-to-Source Voltage

Continuous Drain Current, V

Pulsed Drain Current

Power Dissipation

Linear Derating Factor W/°C Operating Junction and °C

Storage Temperature Range

c f f

@ 10V

GS

@ 10V

GS

Max.

30

± 20

17.2

13.8

135

2.5

1.6

0.02

-55 to + 150

A

W

Thermal Resistance

Parameter Typ. Max. Units

R

θJL

R

θJA

Junction-to-Drain Lead

Junction-to-Ambient

fg

g

––– 20 °C/W

––– 50

Notes  through  are on page 10

www.irf.com 1

6/30/05

IRF8113

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

BV

DSS

∆ΒV

DSS

R

DS(on)

V

GS(th)

∆V

GS(th)

I

DSS

I

GSS

gfs Forward Transconductance 73 ––– ––– S

Q

g

Q

gs1

Q

gs2

Q

gd

Q

godr

Q

sw

Q

oss

R

G

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

Drain-to-Source Breakdown Voltage 30 ––– ––– V

/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.024 ––– V/°C

Static Drain-to-Source On-Resistance ––– 4.7 5.6

mΩ

––– 5.8 6.8

Gate Threshold Voltage 1.5 ––– 2.2 V

Gate Threshold Voltage Coefficient ––– - 5.4 ––– mV/°C

Drain-to-Source Leakage Current ––– ––– 1.0 µA

––– ––– 150

Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

Total Gate Charge ––– 24 36

Pre-Vth Gate-to-Source Charge ––– 6.2 –––

Post-Vth Gate-to-Source Charge ––– 2.0 ––– nC

Gate-to-Drain Charge ––– 8.5 –––

Gate Charge Overdrive ––– 7.3 ––– See Fig. 16

Switch Charge (Q

+ Qgd) ––– 10.5 –––

gs2

Output Charge ––– 10 ––– nC

Gate Resistance ––– 0.8 1.5

Ω

Turn-On Delay Time ––– 13 –––

Rise Time ––– 8.9 –––

Turn-Off Delay Time ––– 17 ––– ns

Fall Time ––– 3.5 –––

Input Capacitance ––– 2910 –––

Output Capacitance ––– 600 ––– pF

Reverse Transfer Capacitance ––– 250 –––

VGS = 0V, ID = 250µA

Reference to 25°C, I

V

GS

V

GS

V

DS

V

DS

V

DS

V

GS

V

GS

V

DS

V

DS

VGS = 4.5V

I

= 13.3A

D

V

DS

V

DD

ID = 13.3A

Clamped Inductive Load

V

GS

V

DS

ƒ = 1.0MHz

Avalanche Characteristics

Parameter Units

E

AS

I

AR

Single Pulse Avalanche Energy

Avalanche Current

c

d

Typ.

–––

Diode Characteristics

Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous Source Current ––– ––– 3.1

(Body Diode) A

Pulsed Source Current ––– ––– 135

(Body Diode)

c

Diode Forward Voltage ––– ––– 1.0 V

Reverse Recovery Time ––– 34 51 ns

Reverse Recovery Charge ––– 21 32 nC

MOSFET symbol

showing the

integral reverse

p-n junction diode.

TJ = 25°C, IS = 13.3A, VGS = 0V

= 25°C, IF = 13.3A, VDD = 10V

T

J

di/dt = 100A/µs

2 www.irf.com

Conditions

= 1mA

D

= 10V, ID = 17.2A

= 4.5V, ID = 13.8A

e

= VGS, ID = 250µA

= 24V, VGS = 0V

= 24V, VGS = 0V, TJ = 125°C

= 20V

= -20V

= 15V, ID = 13.3A

= 15V

= 10V, VGS = 0V

= 15V, VGS = 4.5V

e

= 0V

= 15V

Max.

48

13.3

Conditions

e

mJ

A

e

IRF8113

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

1000

100

10

D

VGS

TOP 10V

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V BOTTOM 2.5V

2.5V

20µs PULSE WIDTH Tj = 25°C

1

0.01 0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

1000

)

Α

(

t n e

r

100

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

TJ = 150°C

TJ = 25°C

10

V

= 15V

DS

1

2.5 3.0 3.5 4.0

20µs PULSE WIDTH

VGS, Gate-to-Source Voltage (V)

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

1000

100

10

D

VGS

TOP 10V

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V BOTTOM 2.5V

2.5V

20µs PULSE WIDTH Tj = 150°C

1

0.01 0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

2.0

e c n a

t s

i s e

R n O

)

e

d

c

e

r

z

u

i

l

o

a

S

-

m

o

r

t

o

n

N

i

( a

r D

,

) n o

( S D

R

ID = 16.6A

V

= 10V

GS

1.5

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

Vs. Temperature

www.irf.com 3

IRF8113

100000

) F

10000

p

( e

c n a

t

i c a p a

C

1000

, C

100

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

Ciss

Coss

Crss

+ Cgd, C

gs

gd

+ C

ds

iss

C

rss

C

oss

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

12

SHORTED

ds

gd

) V

( e

g a

t

l o V

e c

r u o S

o

t

e

t a

G ,

V

ID= 13.3A

10

8

6

4

S

2

G

0

0 102030405060

Q

VDS= 24V

VDS= 15V

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000.0

) A

(

100.0

t n e

r

r u

C n

i a

r

10.0

D e

s

r e v e

R

1.0

,

D S

I

0.1

TJ = 150°C

TJ = 25°C

0.2 0.4 0.6 0.8 1.0 1.2

VSD, Source-toDrain Voltage (V)

Fig 7. Typical Source-Drain Diode

V

GS

= 0V

1000

) A

( t

100

n e

r

r u

C e

c

r u

10

o S

o

t

n

i a

r

1

D ,

D

I

Tc = 25°C Tj = 150°C Single Pulse

0.1

0.1 1.0 10.0 100.0 1000.0

V

OPERATION IN THIS AREA LIMITED BY RDS(on)

, Drain-toSource Voltage (V)

DS

100µsec

1msec

10msec

Fig 8. Maximum Safe Operating Area

Forward Voltage

4 www.irf.com

IRF8113

τ

18

16

14

) A

(

12

t n e

r

10

u C n

i

8

a

r D

,

6

D

I

4

2

0

25 50 75 100 125 150

TJ , Junction Temperature (°C)

Fig 9. Maximum Drain Current Vs.

Case Temperature

2.2

)

2.0

V

( e

g a

t

l

1.8

o V

d

l o

1.6

h s e

r h

t

1.4

e

t a

G

1.2

) h

t

( S G

1.0

V

0.8

-75 -50 -25 0 25 50 75 100 125 150

ID = 250µA

TJ , Temperature ( °C )

Fig 10. Threshold Voltage Vs. Temperature

100

D = 0.50

)

10

A J h

t

Z (

1

e s n o p s e

0.1

R l a

m

r e h T

0.01

0.001

1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100

0.20

0.10

0.05

0.02

0.01

SINGLE PULSE ( THERMAL RESPONSE )

τ

J

τ

J

τ

1

τ

1

Ci= τi/Ri

R

1

2

R

1

τ

2

τ

3

R

2

3

τ

3

τ

2

3

Ri (°C/W) τi (sec)

4

R

4

0.924 0.000228

τ

C

4

τ

4

13.395 0.1728

22.046 1.5543

τ

14.911 22.5

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthja + Tc

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

www.irf.com 5

IRF8113

A

15V

V

DS

R

G

V

20V

GS

L

D.U.T

I

AS

0.01

t

p

Ω

DRIVER

+

-

V

DD

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

I

AS

Fig 12b. Unclamped Inductive Waveforms

200

) J

m

( y

g

160

r e n E

e h c

120

n a

l a v A

e

80

s

l u P

e

l g n

i

40

S

, S A

E

0

25 50 75 100 125 150

I

TOP

8.2A

BOTTOM

Starting TJ, Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

V

DS

7.3A

L

D

V

13.3A

DD

D

+

-

D.U.T

Current Regulator

Same Type as D.U.T.

50KΩ

12V

.2µF

V

GS

.3µF

D.U.T.

3mA

I

G

Current Sampling Resistors

I

D

Fig 13. Gate Charge Test Circuit

Fig 14a. Switching Time Test Circuit

+

V

DS

-

V

DS

90%

10%

V

GS

Fig 14b. Switching Time Waveforms

V

GS

Pulse Width < 1µs

Duty Factor < 0.1%

t

d(on)

r

t

d(off)

t

f

6 www.irf.com

IRF8113





Reverse Recovery Current

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied Voltage

+

-

Period

P.W.

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

www.irf.com 7

IRF8113

)

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R MOSFET, but these conduction losses are only about one half of the total losses.

Power losses in the control switch Q1 are given by;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

= I

()

rms

⎛ ⎜

+ I ×

⎝

+ Qg× Vg× f

()

Q

⎛

+

⎝

This simplified loss equation includes the terms Q and Q

charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q Fig 16.

the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I gins to change. Minimizing Q reducing switching losses in Q1.

put capacitance of the MOSFET during every switching cycle. Figure A shows how Q parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.

which are new to Power MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the out-

oss

+ P

2

× R

ds(on )

Q

gd

× Vin× f

i

g

oss

×Vin× f

2

at which time the drain voltage be-

dmax

switching

⎞ ⎟

⎠

⎞ ⎠

and Q

gs1

+ P

+ I ×

+ P

drive

⎛

Q

gs2

⎜

i

⎝

g

, can be seen from

gs2

is a critical factor in

gs2

is formed by the

oss

of the

ds(on)

output

× Vin× f

Synchronous FET

The power loss equation for Q2 is approximated

by;

P

= P

loss

conduction

P

= I

loss

+ Qg× Vg× f

+

rms

()

⎛

Q

⎜ ⎝

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R

portant characteristic; however, once again the im-

⎞ ⎟

portance of gate charge must not be overlooked since

⎠

it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q verse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

gs2

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Q potential for Cdv/dt turn on.

Figure A: Q

+ P

2

× R

ds(on)()

oss

×Vin× f

2

must be minimized to reduce the

gs1

Characteristic

oss

drive

*

+ P

output

⎞

+ Qrr× Vin× f

(

⎠

ds(on)

oss

is an im-

and re-

8 www.irf.com

SO-8 Package Details

D B

A

87

6

E

e

6X

5

65

4312

e1

0.25 [.010]

IRF8113

.0688

.0098

.020

.1968

.1574

.2440

.0196

.050

8°

MI L LI ME T E R SINCHES

MI N MAX

1.35

1.75

0.10

0.25

0.33

0.51

4.80

5.00

3.80

4.00

1.27 BASIC

5.80

6.20

0.25

0.50

0.40

1.27

8°

0°

DIM

MI N MAX

A

.0532

A1

.0040

b

.013

H

A

C

y

c .0075 .0098 0.19 0.25

D

.189

E

.1497

e

.050 BASIC

.025 BASIC 0.635 B AS IC

e1

H

.2284

K

.0099

L

.016

y

0°

K x 45°

8X b

0.25 [.010] C A B

A1

NOTE S:

1. DIMENSIONING & T OL ERANCING PER AS ME Y14.5M-1994.

2. CONT ROLL ING DIMENS ION: MILLIMETER

3. DIMENSI ONS ARE SHOWN IN MIL LIMETE RS [INCHES].

4. OU T L I NE CONF OR MS T O JE DE C OUT L INE MS -0 12 AA.

5 DIMENS ION DOE S NOT INCLUDE MOLD PR OT RU SIONS. MOLD PROTR US IONS NOT T O E XCE ED 0.15 [.006].

6 DIMENS ION DOE S NOT INCLUDE MOLD PR OT RU SIONS. MOLD PROTR US IONS NOT T O E XCE ED 0.25 [.010].

7 DIMENS ION IS THE LE NGT H OF L EAD FOR S OLDE RING TO A SU BS T RATE.

SO-8 Part Marking

EXAMPLE: THIS IS AN IRF7101 (MOSFET)

INTERNATIONAL

RECTIFIER

LOGO

0.10 [.004]

F7101

XXXX

8X L

7

8X c

FOOTPRINT

8X 0.72 [.028]

6.46 [.255]

3X 1.27 [.050]

8X 1.78 [.070]

DAT E CODE (YWW) P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

Y = LAST DIGIT OF THE YEAR WW = WE E K A = AS S E MB L Y S IT E CODE

LOT CODE

PART NUMBER

www.irf.com 9

IRF8113

SO-8 Tape and Reel

TERMINAL NUMBER 1

12.3 ( .484 )

11.7 ( .461 )

8.1 ( .318 )

7.9 ( .312 )

NOTES:

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

330.00 (12.992) MAX.

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature.

 Starting T

RG = 25Ω, I

= 25°C, L = 0.54mH

J

= 13.3A.

AS

 Pulse width ≤ 400µs; duty cycle ≤ 2%.  When mounted on 1 inch square copper board  R

is measured at TJ approximately 90°C

θ

This product has been designed and qualified for the Industrial market.

FEED DIRECTION

14.40 ( .566 )

12.40 ( .488 )

Data and specifications subject to change without notice.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.6/05

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