Datasheet irf7832 Datasheet

Applications

A

l Synchronous MOSFET for Notebook

Processor Power

l Synchronous Rectifier MOSFET for

Isolated DC-DC Converters in Networking Systems

Benefits

l Very Low R l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage

DS(on)

at 4.5V V

GS

and Current

l 20V V

Max. Gate Rating

GS

Absolute Maximum Ratings

Parameter Units

V

DS

V

GS

I

@ TA = 25°C

D

I

@ TA = 70°C

D

I

DM

PD @TA = 25°C P

@TA = 70°C

D

T

J

T

STG

Drain-t o-Source Voltage V Gate-to-Source Volt age

Conti n uous Drai n Cur r e nt, V Conti n uous Drai n Cur r e nt, V

Pulsed Drain Current Power Dissipation W

Power Dissipation Linear D er ating Factor W/°C

Operating Junction and °C Stor ag e Temperat ur e Ra ng e

c

@ 10V

GS

@ 10V

GS

V

DSS

30V

S S

S

R

4.0m

1

2

3

4

Top View

PD - 94594A

IRF7832

HEXFET® Power MOSFET

DS(on)

:

max

@VGS = 10V

A

8

D

7

D

6

D

5

DG

Max.

30

± 20

20 16

160

2.5

1.6

0.02

-55 to + 150

Qg

34nC

SO-8

A

Thermal Resistance

Parameter Typ. Max. Units

R

JL

θ

R

JA

θ

Junction- to-Drain Lead ––– 20 °C/W Junction-to-Ambient

f

––– 50

Notes  through  are on page 10

www.irf.com 1

03/07/03

IRF7832

/

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

BV

DSS

∆ΒV

DSS

R

DS(on)

V

GS(th)

∆V

GS(th)

I

DSS

I

GSS

gfs Forward Transconductance 77 ––– ––– S Q

g

Q

gs1

Q

gs2

Q

gd

Q

godr

Q

sw

Q

oss

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

Drain-to-Sou r c e Br e akdown Voltage 30 ––– ––– V

∆T

Breakdown Voltag e Temp. Coef fi cient ––– 0.023 ––– V/°C

J

Stat ic D r ai n- to-Sou rce On-Res i s tance ––– 3.1 4.0

––– 3.7 4.8 Gate Thr es hold Voltage 1.39 ––– 2.32 V Gate Th res hold Voltage Coef ficien t ––– 5.7 ––– mV / ° C Drain-to-Sou r c e Le akage Cur rent ––– ––– 1.0 µA

––– ––– 150 Gate-to-Sour c e Forward Lea k age ––– ––– 100 nA Gate-to-Sou rce Reverse Leaka ge ––– ––– -100

Total Gate Charge ––– 34 51 Pre-Vth Gate-to-Source Charge ––– 8.6 ––– Post-Vth Gate-to-Source Charge ––– 2.9 ––– nC Gate-to-Drain Charge ––– 12 ––– Gate Cha r ge Ov e r drive ––– 10.5 ––– See Fig. 16 Switch Charge (Q

gs2

+ Qgd)

––– 14.9 ––– Output Charge ––– 23 ––– nC Turn-On Delay Time ––– 6.7 ––– Rise Time ––– 12.3 ––– Turn-Off Delay Time ––– 13 – –– n s Fall Time ––– 21 ––– Input Capacitance ––– 4310 ––– Outpu t C ap ac itance ––– 990 ––– pF Reverse Transfer Capacitance ––– 450 –––

VGS = 0V, ID = 250µA Referen ce to 25°C, I V

mΩ

= 10V, ID = 20A

GS

V

= 4.5V, ID = 16A

GS

V

= VGS, ID = 250µA

DS

= 24V, VGS = 0V

V

DS

= 24V, VGS = 0V, TJ = 125°C

V

DS

V

= 20V

GS

= -20V

V

GS

= 15V, ID = 16A

V

DS

V

= 15V

DS

VGS = 4.5V I

= 16A

D

VDS = 16V, VGS = 0V V

= 15V, VGS = 4.5V

DD

= 16A

I

D

Clampe d I n ductiv e Load

= 0V

V

GS

= 15V

V

DS

ƒ = 1.0MHz

Conditions

= 1mA

D

e

Avalanche Characteristics

Parameter Units

E

AS

I

AR

Single Pulse Avala nche Energy Avalanche Current

c

d

Typ.

––– –––

Max.

260

16

mJ

A

Diode Ch aracteristics

Paramete r Min. Typ . Max. Units

I

S

Contin uous Source Current ––– ––– 3.1 (Body Diode) A

I

SM

V

SD

t

rr

Q

rr

t

on

Pulsed Source Current ––– ––– 160 (Body Diode)

c

Diode Forward Voltage ––– ––– 1.0 V Reverse Recovery Time ––– 41 62 ns Reverse Recovery Charge ––– 39 59 nC Forward Turn-On Time In trinsic turn-on time is negligible (turn-on is dominated by LS+LD)

MOSFET symbol showing the

integral reverse p-n junct ion diode.

TJ = 25°C, IS = 16A, VGS = 0V

= 25°C, IF = 16A, VDD = 10V

T

J

di/dt = 100A/µs

Conditions

D

G

S

e

2 www.irf.com

IRF7832

1000

TOP 10V

)

100

A

(

t

n

e

r

u C

10

e

c

r

u

o S

-

1

o

t

-

n

i

a

r D

,

0.1

D

I

2.25V

BOTTOM 2.25V

20µs PULSE WIDTH Tj = 25°C

0.01

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

)

Α

(

t

100

n

e

r

u C e

c

r

u

o S

-

o

t

-

n

i

a

r D

,

D

I

TJ = 150°C

10

TJ = 25°C

1

V

= 15V

DS

20µs PULSE WIDTH

0

2.0 2.5 3.0 3.5 4.0

VGS, Gate-t o-Source Voltage (V)

VGS

5.0V

4.5V

3.5V

3.0V

2.7V

2.5V

) A

(

t

n

e

r

u C e

c

r

u

o S

-

o

t

-

n

i

a

r D

, I

D

1000

100

TOP 10V

BOTTOM 2.25V

10

2.25V

20µs PULSE WIDTH

VGS

5.0V

4.5V

3.5V

3.0V

2.7V

2.5V

Tj = 150°C

1

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

2.0

e

c

n

a

t

s

i

s

e R n O e

c

r

)

u

d

o

e

z

S

i

l

-

a

o

t

m

-

r

n

i

o

a

N

r

(

D ,

)

n

o

( S D

R

I

= 16A

D

VGS = 4.5V

1.5

1.0

0.5

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ, Junction Temperature (°C )

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

Vs. Temperature

www.irf.com 3

IRF7832

100000

) F

10000

p

(

e

c

n

a

t

i

c

a

p

a C

,

1000

C

100

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

+ Cgd, C

iss

gs

C

= C

rss

gd

C

= C

ds

+ C

oss

VDS, Drain-to-Source Voltage (V )

gd

SHORTED

ds

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000

6

ID= 16A

)

5

V

( e

g

a

t

l

4

o V

e

c

C

iss

C

oss

C

rss

r

u

3

o S

-

o

t

-

e

t

2

a G

,

S G

1

V

0

0 1020304050

VDS= 24V VDS= 15V

Q

Total G ate Charge (nC)

G

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

)

Α

(

t

100

n

e

r

u C n

i

a

r D e

s

r

e

v

e R

,

D S

I

TJ = 150°C

10

1

0.1

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 V

, Source-to-Drain Voltage (V)

SD

Fig 7. Typical Source-Drain Diode

TJ = 25°C

V

GS

= 0V

) A

(

t

n

e

r

100

u C e

c

r

u

o S

-

o

t

-

n

10

i

a

r D ,

D

Tc = 25°C

I

Tj = 150°C Single Pulse

1

1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

100µsec

1msec

10msec

Forward Voltage

4 www.irf.com

IRF7832

24

20

) A

(

16

t

n

e

r

u

12

C n

i

a

r D

8

,

D

I

4

0

25 50 75 100 125 150

TC , Case Temper ature (°C)

Fig 9. Maximum Drain Current Vs.

Case Temperature

100

0.7

) V

( e

0.6

g

a

t

l

o V

d

l

0.5

o

h

s

e

r

h T

0.4

e

t

a G

,

)

h

t

(

0.3

S G

V

0.2

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Temperat ure (°C)

ID = 250µA

Fig 10. Threshold Voltage Vs. Temperature

)

A

J

h

t

Z (

e

s

n

o

p

s

e R

l

a m

r

e

h T

0.01

D = 0.50

10

0.1

0.20

0.10

0.05

1

0.02

0.01

SINGLE PULSE ( THERMAL RESPONSE )

1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100

t1 , Rectangular Pulse Dur ation (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

www.irf.com 5

IRF7832

A

15V

L

D.U.T

I

AS

Ω

0.01

t

p

R

V

20V

V

DS

G

GS

Fig 12a. Unclamped Inductive Test Circuit

t

p

DRIVER

V

(BR)DSS

+

-

600

)

J m

( y

500

g

r

e

n E

e

400

h

c

n

a

V

DD

l

a

v

300

A e

s

l

u P

200

e

l

g

n

i S

,

100

S A

E

0

25 50 75 100 125 150

TOP 7.0A BOTTOM 16A

I

D

13A

Starting TJ , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

I

AS

V

DS

L

D

Fig 12b. Unclamped Inductive Waveforms

V

DD

D.U.T

Current Regulator

Same Type as D.U.T.

50KΩ

12V

.2µF

.3µF

D.U.T.

V

GS

3mA

I

G

Current Sampling Resistors

I

D

Fig 13. Gate Charge Test Circuit

Fig 14a. Switching Time Test Circuit

+

V

DS

-

Fig 14b. Switching Time Waveforms

V

GS

Pulse Width < 1µs

Duty Factor < 0.1%

V

DS

90%

10% V

GS

t

d(on)tr

t

d(off)tf

6 www.irf.com

IRF7832

Reverse Recovery Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

D.U.T

+



-

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

+



V

DD

R

G

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

-

Re-Applied Voltage

Inductor Curent

* V

GS

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P.W.

Period

VGS=10V

V

DD

I

SD

*

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

www.irf.com 7

IRF7832

)

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R MOSFET, but these conduction losses are only about one half of the total losses.

Power losses in the control switch Q1 are given by;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

= I

()

rms

 

+ I ×



+ Qg× Vg× f

()

Q



+



This simplified loss equation includes the terms Q and Q

charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q Fig 16.

the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I gins to change. Minimizing Q reducing switching losses in Q1.

put capacitance of the MOSFET during every switching cycle. Figure A shows how Q parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.

which are new to Power MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the out-

oss

+ P

2

× R

ds(on )

Q

gd

× Vin× f

i

g

oss

×Vin× f

2

at which time the drain voltage be-

dmax

switching

 



 

and Q

gs1

+ P

+ I ×

+ P

drive



Q

gs2



i



g

, can be seen from

gs2

is a critical factor in

gs2

is formed by the

oss

of the

ds(on)

output

× Vin× f

Synchronous FET

The power loss equation for Q2 is approximated

by;

P

= P

loss

conduction

P

= I

loss

+ Qg× Vg× f

+

rms

()



Q

 

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R

portant characteristic; however, once again the im-

 

portance of gate charge must not be overlooked since



it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q verse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

gs2

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Q potential for Cdv/dt turn on.

Figure A: Q

+ P

2

× R

ds(on)()

oss

×Vin× f

2

must be minimized to reduce the

gs1

Characteristic

oss

drive

*

+ P

output



+ Qrr× Vin× f

(



ds(on)

oss

is an im-

and re-

8 www.irf.com

SO-8 Package Details

IRF7832

D B

8X b

5

65

4312

e1

A1

H

0.25 [.010]

A

C

0.10 [.004 ]

A

87

6

E

e

6X

0.25 [.010 ] C A B

NOTES :

1. DIMENSIONING & TOL ERANCING PER ASME Y14.5M-1994.

2. CONTROL L ING DIME NS ION: MILLI MET ER

3. DI MENS IONS ARE S H OWN IN MILL IMET ER S [INCHE S ].

4. OUT L I NE CONF OR MS T O JE DE C OUT L I NE MS -01 2AA.

5 DIME NS ION DOES NOT INCLUDE MOLD PR OT RU SI ONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].

6 DIME NS ION DOES NOT INCLUDE MOLD PR OT RU SI ONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].

7 DIME NSION IS T HE LENGT H OF LEAD FOR SOLDERING TO A S UB STRAT E.

y

3X 1.27 [.050]

DIM

MI N MAX

A

.0532

A1

b

c .0075 .0098 0.19 0. 25

D

E

e

e1

H

K

L

y

K x 45°

8X L

7

6.46 [.255]

.0688

.0040

.0098

.013

.020

.189

.1968

.1497

.1574

.050 BASIC

.025 BASIC 0.635 BASIC

.2284

.2440

.0099

.0196

.016

.050

0°

8°

8X c

F OOT P R I NT

8X 0.72 [.028]

MILLIMETERSINCHES

MIN MAX

1.35

1.75

0.10

0.25

0.33

0.51

4.80

5.00

3.80

4.00

1.27 B ASIC

5.80

6.20

0.25

0.50

0.40

1.27

0°

8°

8X 1.78 [.070]

SO-8 Part Marking

EXAMPLE : T HIS IS AN IR F 7101 (MOS F E T )

DAT E CODE (YWW) Y = LAS T DIGIT OF T HE YE AR

YWW XXXX

INTERNATIONAL

F7101

RECTIFIER

LOGO

www.irf.com 9

WW = WE E K

LOT CODE

PART NUMBER

IRF7832

SO-8 Tape and Reel

TERMI NA L NU MBER 1

12.3 ( .484 )

11.7 ( .461 )

8.1 ( .318 )

7.9 ( .312 )

NOTES:

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).

3. OUTLINE CONFORMS T O EIA-481 & EI A-541.

NOTES :

1. CONTROLLING DIMENSION : MIL L IMETER.

2. OUTLINE CO NF O RMS TO EIA-481 & EIA-541.

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature.

 Starting T

RG = 25Ω, I

= 25°C, L = 2.0mH

J

= 16A.

AS

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

330.00 (12.992) MAX.

FEED DIRECTION

14.40 ( .566 )

12.40 ( .488 )

 When mounted on 1 inch square copper board

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.03/03

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