l Switch Mode Power Supply ( SMPS )
l Uninterruptable Power Supply
l High speed power switching
l Lead-Free
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss specified ( See AN 1001)
Absolute Maximum Ratings
ParameterMax.Units
ID @ TC = 25°CContinuous Drain Current, VGS @ 10V10
ID @ TC = 100°CContinuous Drain Current, VGS @ 10V6.3A
I
DM
PD @TC = 25°CPower Dissipation125W
V
GS
dv/dtPeak Diode Recovery dv/dt 5.9V/ns
T
J
T
STG
Pulsed Drain Current 40
Linear Derating Factor1.0W/°C
Gate-to-Source Voltage ± 30V
Operating Junction and-55 to + 150
Storage Temperature Range
Soldering Temperature, for 10 seconds300 (1.6mm from case )
Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)
V
DSS
Rds(on) maxI
400V0.55Ω10A
TO-220AB
SDG
°C
D
Typical SMPS Topologies:
l Single transistor Flyback Xfmr. Reset
l Single Transistor Forward Xfmr. Reset ( Both for US Line Input only )
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRF740APbF
A
Document Number: 91051
www.vishay.com
6
15V
DRIVER
+
-
V
R
G
20V
V
DS
t
L
D.U.T
I
AS
Ω
0.01
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
3mA
.3µF
D.U.T.
+
V
DS
-
DD
1400
1200
TOP
BOTTOM
1000
800
600
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
255075100125150
Starting T , Junction Temperature ( C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
580
)
V
560
(
e
g
a
t
l
o
V
540
e
h
c
n
a
l
a
520
v
A
,
v
a
S
500
D
V
480
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
I
, Avalanche Current ( A)
AV
I
D
4.5A
6.3A
10A
°
I
I
Current Sampling Resistors
D
G
Fig 13b. Gate Charge Test Circuit
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Page 7
IRF740APbF
Document Number: 91051
www.vishay.com
7
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P. W .
+
+
V
DD
-
VGS=10V
*
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. ISDWaveform
Body Diode Forward
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
Fig 14. For N-Channel HEXFETS
Current
di/dt
Diode Recovery
dv/dt
V
DD
I
SD
Page 8
IRF740APbF
Document Number: 91051
www.vishay.com
8
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
2.87 (. 113)
2.62 (. 103)
15.24 (.600)
14.84 (.584)
14.09 (. 555)
13.47 (. 530)
10.29 (.405)
1 2 3
6.47 (.255)
6.10 (.240)
4
1.15 (.0 45)
MIN
4.06 ( .160)
3.55 ( .140)
3.78 (.1 49)
3.54 (.1 39)
- A -
4.69 (.1 85)
4.20 (.1 65)
- B -
1.32 (.052)
1.22 (.048)
HEXFET
1- GATE
2- DRAIN
3- S OURCE
4- DRAIN
LEAD ASSI GNMENTS
LEAD ASSIGNMENTS 1 -GATE 2 -DRAIN 3 -SOURCE 4 -DRAIN
IGBTs, C oPACK
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
0.93 (. 037)
3X
1.40 (.055)
3X
1.15 (.045)
2.54 (.1 00)
NOTES:
1 DIMENSION ING & TOLER ANC ING PER AN SI Y14 .5M, 19 82. 3 O UTLINE CONFOR MS TO JE DEC O UTLIN E TO-220A B.
2 CONTROL LING D IMENSION : INC H 4 HEAT SINK & LE AD ME ASUR EME NTS DO NOT INCLUDE BURRS.
2X
0.69 (. 027)
0.36 (.014) M B A M
0.55 (. 022)
3X
0.46 (. 018)
2.92 (. 115)
2.64 (. 104)
TO-220AB Part Marking Information
EXAMPLE:
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting T
RG = 25Ω, I
I
≤ 10A, di/dt ≤ 330A/µs, V
SD
TJ ≤ 150°C
T HIS IS AN IRF 1010
LOT CODE 1789
ASS EMBL E D ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
= 25°C, L = 12.6mH
J
= 10A. (See Figure 12)
AS
DD
≤ V
(BR)DSS
INT ER NAT IONAL
RECTIF IER
LOGO
ASSEMBLY
LOT CODE
Pulse width ≤ 300µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
oss
while V
is rising from 0 to 80% V
DS
,
Data and specifications subject to change without notice.
PAR T NUMBER
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
DSS
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
11/03
Page 9
Legal Disclaimer Notice
Vishay
Notice
The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of
International Rectifier’s Power Control Systems (PCS) business, which closed in April 2007. Specifications of the
products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below.
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or
anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
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are registered trademarks of International Rectifier Corporation in the U.S. and other countries. All other product
names noted herein may be trademarks of their respective owners.
®
, IR®, the IR logo, HEXFET®, HEXSense®, HEXDIP®, DOL®, INTERO®, and POWIRTRAIN