Datasheet irf740a Datasheet

Page 1
PD- 94828
Document Number: 91051
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1
SMPS MOSFET
IRF740APbF
HEXFET® Power MOSFET
Applications
l Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching l Lead-Free
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss specified ( See AN 1001)
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 10 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 6.3 A I
DM
PD @TC = 25°C Power Dissipation 125 W
V
GS
dv/dt Peak Diode Recovery dv/dt 5.9 V/ns T
J
T
STG
Pulsed Drain Current 40
Linear Derating Factor 1.0 W/°C Gate-to-Source Voltage ± 30 V
Operating Junction and -55 to + 150 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)
V
DSS
Rds(on) max I
400V 0.55Ω 10A
TO-220AB
SDG
°C
D
Typical SMPS Topologies:
l Single transistor Flyback Xfmr. Reset l Single Transistor Forward Xfmr. Reset ( Both for US Line Input only )
Notes through are on page 8
11/10/03
Page 2
IRF740APbF
Document Number: 91051
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2
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 61 ––– VGS = 0V, VDS = 0V to 320V
oss
Avalanche Characteristics
E
AS
I
AR
E
AR
Thermal Resistance
R
θJC
R
θCS
R
θJA
Diode Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Drain-to-Source Breakdown Voltage 400 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient
J
––– 0.48 ––– V/°C Reference to 25°C, ID = 1mA Static Drain-to-Source On-Resistance ––– ––– 0.55 Ω VGS = 10V, ID = 6.0A Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 320V, VGS = 0V, TJ = 125°C Gate-to-Source Forward Leakage ––– ––– 100 V Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 400V, VGS = 0V
µA
= 30V
GS
nA
V
= -30V
GS
Parameter Min. Typ. Max. Units Conditions Forward Transconductance 4.9 ––– ––– S VDS = 50V, ID = 6.0A Total Gate Charge ––– ––– 36 ID = 10A Gate-to-Source Charge ––– ––– 9.9 nC VDS = 320V Gate-to-Drain ("Miller") Charge ––– ––– 16 VGS = 10V, See Fig. 6 and 13 Turn-On Delay Time ––– 10 ––– VDD = 200V Rise Time ––– 35 ––– ID = 10A Turn-Off Delay Time ––– 24 ––– RG = 10Ω
ns
Fall Time ––– 22 ––– RD = 19.5Ω,See Fig. 10 Input Capacitance ––– 1030 ––– VGS = 0V Output Capacitance ––– 170 ––– VDS = 25V Reverse Transfer Capacitance ––– 7.7 ––– pF ƒ = 1.0MHz, See Fig. 5 Output Capacitance ––– 1490 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz Output Capacitance ––– 52 ––– VGS = 0V, VDS = 320V, ƒ = 1.0MHz
Parameter Typ. Max. Units
Single Pulse Avalanche Energy ––– 630 mJ Avalanche Current ––– 10 A Repetitive Avalanche Energy ––– 12.5 mJ
Parameter Typ. Max. Units
Junction-to-Case ––– 1.0 Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W Junction-to-Ambient ––– 62
Parameter Min. Typ. Max. Units Conditions Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode)
––– –––
––– –––
Diode Forward Voltage ––– ––– 2.0 V TJ = 25°C, IS = 10A, VGS = 0V Reverse Recovery Time ––– 240 360 ns TJ = 25°C, IF = 10A Reverse RecoveryCharge ––– 1.9 2.9 µC di/dt = 100A/µs  Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
10
40
showing the
A
p-n junction diode.
D
G
S
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IRF740APbF
Document Number: 91051
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3
100
10
1
0.1
D
I , Drain-to-Source Current (A)
0.01
0.1 1 10 100
100
VGS
TOP
15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20µs PULSE WIDTH T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
°
100
10
1
TOP
BOTTOM
VGS 15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
°
T = 150 C
0.1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
10A
10
1
D
I , Drain-to-Source Current (A)
0.1
4.0 5.0 6.0 7.0 8.0 9.0 10.0
°
T = 150 C
J
°
T = 25 C
J
V = 50V
DS
20µs PULSE WIDTH
V , Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V =
GS
°
10V
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IRF740APbF
Document Number: 91051
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4
100000
10000
) F p
( e
1000
c n a
t
i c a p
100
a C
, C
10
1
1 10 100 1000
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
gs
gd
ds
Ciss
Coss
Crss
+ Cgd, C
+ C
gd
iss
C
rss
C
oss
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
SHORTED
ds
20
I =
10A
D
V = 320V
DS
V = 200V
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
DS
V = 80V
DS
FOR TEST CIRCUIT
0
0 10 20 30 40
Q , Total Gate Charge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
10us
10
°
T = 150 C
J
°
T = 25 C
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4
V ,Source-to-Drain Voltage (V)
SD
J
V = 0 V
GS
Fig 7. Typical Source-Drain Diode
Forward Voltage
10
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 150 C Single Pulse
1
10 100 1000
°
J
V , Drain-to- Source Voltage (V)
DS
100us
1ms
10ms
Fig 8. Maximum Safe Operating Area
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10.0
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5
8.0
6.0
4.0
D
I , Drain Current (A)
2.0
0.0 25 50 75 100 125 150
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
IRF740APbF
R
D.U.T.
t
d(off)tf
D
V
DS
V
GS
R
G
10V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10% V
GS
t
d(on)tr
Fig 10b. Switching Time Waveforms
+
V
DD
-
10
1
thJC
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Thermal Response (Z )
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
0.001
0.00001 0.0001 0.001 0.01 0.1 1 10
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRF740APbF
A
Document Number: 91051
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6
15V
DRIVER
+
-
V
R
G
20V
V
DS
t
L
D.U.T
I
AS
Ω
0.01
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
3mA
.3µF
D.U.T.
+
V
DS
-
DD
1400
1200
TOP
BOTTOM
1000
800
600
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Junction Temperature ( C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
580
) V
560
( e
g a
t
l o V
540
e h c n a
l a
520
v A ,
v a S
500
D
V
480
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
I
, Avalanche Current ( A)
AV
I
D
4.5A
6.3A 10A
°
I
I
Current Sampling Resistors
D
G
Fig 13b. Gate Charge Test Circuit
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Page 7
IRF740APbF
Document Number: 91051
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7
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P. W .
+
+
V
DD
-
VGS=10V
*
Reverse Recovery Current
Re-Applied Voltage
D.U.T. ISDWaveform
Body Diode Forward
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
Fig 14. For N-Channel HEXFETS
Current
di/dt
Diode Recovery
dv/dt
V
DD
I
SD
Page 8
IRF740APbF
Document Number: 91051
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8
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
2.87 (. 113)
2.62 (. 103)
15.24 (.600)
14.84 (.584)
14.09 (. 555)
13.47 (. 530)
10.29 (.405)
1 2 3
6.47 (.255)
6.10 (.240)
4
1.15 (.0 45) MIN
4.06 ( .160)
3.55 ( .140)
3.78 (.1 49)
3.54 (.1 39)
- A -
4.69 (.1 85)
4.20 (.1 65)
- B -
1.32 (.052)
1.22 (.048)
HEXFET
1- GATE 2- DRAIN 3- S OURCE 4- DRAIN
LEAD ASSI GNMENTS
LEAD ASSIGNMENTS 1 - GAT E 2 - DRA IN 3 - SOU RCE 4 - DRA IN
IGBTs, C oPACK
1- GATE 2- COLLECTOR 3- EMITTER 4- COLLECTOR
0.93 (. 037)
3X
1.40 (.055)
3X
1.15 (.045)
2.54 (.1 00)
NOTES:
1 DIMENSION ING & TOLER ANC ING PER AN SI Y14 .5M, 19 82. 3 O UTLINE CONFOR MS TO JE DEC O UTLIN E TO-220A B. 2 CONTROL LING D IMENSION : INC H 4 HEAT SINK & LE AD ME ASUR EME NTS DO NOT INCLUDE BURRS.
2X
0.69 (. 027)
0.36 (.014) M B A M
0.55 (. 022)
3X
0.46 (. 018)
2.92 (. 115)
2.64 (. 104)
TO-220AB Part Marking Information
EXAMPLE:
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
 Starting T
RG = 25Ω, I
I
≤ 10A, di/dt ≤ 330A/µs, V
SD
TJ ≤ 150°C
T HIS IS AN IRF 1010
LOT CODE 1789 ASS EMBL E D ON WW 19, 1997 IN THE ASSEMBLY LINE "C"
Note: "P" in assembly line position indicates "Lead-Free"
= 25°C, L = 12.6mH
J
= 10A. (See Figure 12)
AS
DD
≤ V
(BR)DSS
INT ER NAT IONAL
RECTIF IER
LOGO
ASSEMBLY LOT CODE
Pulse width ≤ 300µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
oss
while V
is rising from 0 to 80% V
DS
,
Data and specifications subject to change without notice.
PAR T NUMBER
DATE CODE YEAR 7 = 1997 WEEK 19 LINE C
DSS
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
11/03
Page 9
Legal Disclaimer Notice
Vishay
Notice
The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of International Rectifier’s Power Control Systems (PCS) business, which closed in April 2007. Specifications of the products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below.
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
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®
, IR®, the IR logo, HEXFET®, HEXSense®, HEXDIP®, DOL®, INTERO®, and POWIRTRAIN
®
Document Number: 99901 www.vishay.com Revision: 12-Mar-07 1
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