Datasheet irf730as-l Datasheet

Page 1
SMPS MOSFET
Document Number: 91046
www.vishay.com
1
IRF730AS/LPbF
PD-95114
HEXFET® Power MOSFET
Applications
l Switch Mode Power Supply (SMPS) l Uninterruptable Power Supply l High speed power switching l Lead-Free
V
DSS
Rds(on) max I
400V 1.0Ω 5.5A
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified (See AN1001)
2
D Pak
TO-262
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 5.5 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 3.5 A I
DM
PD @TC = 25°C Power Dissipation 74 W
V
GS
dv/dt Peak Diode Recovery dv/dt  4.6 V/ns T
J
T
STG
Pulsed Drain Current  22
Linear Derating Factor 0.6 W/°C Gate-to-Source Voltage ± 30 V
Operating Junction and -55 to + 150 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
D
Typical SMPS Topologies:
l Single Transistor Flyback Xfmr. Reset l Single Transistor Forward Xfmr. Reset
(Both US Line input only).
Notes  through are on page 10
3/16/04
Page 2
IRF730AS/LPbF
Document Number: 91046
www.vishay.com
2
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 45 ––– VGS = 0V, VDS = 0V to 320V 
oss
Drain-to-Source Breakdown Voltage 400 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient
J
––– 0.5 ––– V/°C Reference to 25°C, ID = 1mA Static Drain-to-Source On-Resistance ––– ––– 1.0 Ω VGS = 10V, ID = 3.3A Gate Threshold Voltage 2.0 ––– 4.5 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 320V, VGS = 0V, TJ = 125°C Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 400V, VGS = 0V
µA
nA
VGS = -30V
Parameter Min. Typ. Max. Units Conditions Forward Transconductance 3.1 ––– ––– S VDS = 50V, ID = 3.3A Total Gate Charge ––– ––– 22 ID = 3.5A Gate-to-Source Charge ––– ––– 5.8 nC VDS = 320V Gate-to-Drain ("Miller") Charge ––– ––– 9.3 VGS = 10V, See Fig. 6 and 13  Turn-On Delay Time ––– 10 ––– VDD = 200V Rise Time ––– 22 ––– ID = 3.5A Turn-Off Delay Time ––– 20 ––– RG = 12Ω
ns
Fall Time ––– 16 ––– RD = 57Ω,See Fig. 10  Input Capacitance ––– 600 ––– VGS = 0V Output Capacitance ––– 103 ––– VDS = 25V Reverse Transfer Capacitance ––– 4.0 ––– pF ƒ = 1.0MHz, See Fig. 5 Output Capacitance ––– 890 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz Output Capacitance ––– 30 ––– VGS = 0V, VDS = 320V, ƒ = 1.0MHz
Avalanche Characteristics
Parameter Typ. Max. Units
E
AS
I
AR
E
AR
Single Pulse Avalanche Energy ––– 290 mJ Avalanche Current ––– 5.5 A Repetitive Avalanche Energy ––– 7.4 mJ
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
Junction-to-Case ––– 1.7 °C/W Junction-to-Ambient ( PCB Mounted, steady-state)* ––– 40
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode) Diode Forward Voltage ––– ––– 1.6 V TJ = 25°C, IS = 5.5A, VGS = 0V Reverse Recovery Time ––– 370 550 ns TJ = 25°C, IF = 3.5A Reverse RecoveryCharge ––– 1.6 2.4 µC di/dt = 100A/µs  Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
––– –––
––– –––
5.5
22
showing the
A
p-n junction diode.
D
G
S
Page 3
IRF730AS/LPbF
Document Number: 91046
www.vishay.com
3
100
10
1
0.1
D
I , Drain-to-Source Current (A)
0.01
0.1 1 10 100
VGS
TOP
15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
20µs PULSE WIDTH T = 25 C
J
V , Drain-to- Sourc e Voltage (V)
DS
4.5V
°
Fig 1. Typical Output Characteristics
100
100
10
1
TOP
BOTTOM
VGS 15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
0.1
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
°
T = 150 C
0.01
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 2. Typical Output Characteristics
2.5
I =
D
5.5
5.9A
10
1
D
I , Drain-to-Source Current (A)
0.1
4.0 5.0 6.0 7.0 8.0 9.0 10.0
V , Gate-to-Source Voltage (V)
GS
°
T = 150 C
J
T = 25 C
J
°
V = 50V 20µs PULSE WIDTH
DS
Fig 3. Typical Transfer Characteristics
2.0
1.5
1.0
(Normalized)
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V =
GS
°
10V
Page 4
IRF730AS/LPbF
Document Number: 91046
www.vishay.com
4
100000
10000
) F p
( e
1000
c n a
t
i c a p a
100
C ,
C
10
1
1 10 100 1000
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
+ Cgd, C
gs
gd
+ C
ds
gd
C
C
iss
rss
oss
Ciss
Coss
Crss
VDS, Drain-to-Source Voltage (V)
SHORTED
ds
20
5.5
I =
5.9A
D
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
0
0 5 10 15 20 25
Q , Total Gate Charge (nC)
G
V = 320V
DS
V = 200V
DS
V = 80V
DS
FOR TEST CIRCUIT
SEE FIGURE
13
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
10
1
SD
I , Reverse Drain Current (A)
0.1
0.4 0.6 0.8 1.0 1.2
T = 150 C
V ,Source-to-Drain Voltage (V)
SD
°
J
°
T = 25 C
J
V = 0 V
GS
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
OPERATION IN THIS AREA LIMITED
10
1
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 150 C Single Pulse
0.1 10 100 1000
°
J
V , Drain-to-Source Voltage (V)
DS
BY R
DS(on)
10us
100us
1ms
10ms
Fig 8. Maximum Safe Operating Area
Page 5
IRF730AS/LPbF
Document Number: 91046
www.vishay.com
5
6.0
5.0
4.0
3.0
2.0
D
I , Drain Current (A)
1.0
0.0 25 50 75 100 125 150
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
R
V
DS
V
GS
R
G
D
D.U.T.
10V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10% V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
+
V
DD
-
thJC
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
Thermal Response (Z )
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRF730AS/LPbF
A
Document Number: 91046
www.vishay.com
6
15V
DRIVER
+
-
V
R
20V
V
DS
G
t
L
D.U.T
I
AS
Ω
0.01
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
3mA
.3µF
D.U.T.
+
V
DS
-
DD
700
600
TOP
BOTTOM
500
400
300
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Junction Temperature ( C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
610
)
600
V (
e g
590
a
t
l o
V
580
e h c n a
l
570
a v
A ,
v
560
a S D
V
550
540
0.0 1.0 2.0 3.0 4.0 5.0 6.0
I
, Avalanche Current ( A)
AV
I
D
2.5A
3.5A
5.5A
°
I
Current Sampling Resistors
I
D
G
Fig 13b. Gate Charge Test Circuit
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Page 7
IRF730AS/LPbF
Document Number: 91046
www.vishay.com
7
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
P. W .
Period
+
+
V
DD
-
VGS=10V
*
Reverse Recovery Current
Re-Applied Voltage
D.U.T. ISDWaveform
Body Diode Forward
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
Fig 14. For N-Channel HEXFETS
Current
di/dt
Diode Recovery
dv/dt
V
DD
I
SD
Page 8
IRF730AS/LPbF
Document Number: 91046
www.vishay.com
8
2
D
Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 30S WIT H
LOT CODE 8024 AS S E MB LE D ON WW 0 2, 2000 IN THE ASSEMBLY LINE "L"
N ote: "P" in as sem bly line po s i tio n i nd icates "L ead -F ree"
INT ER NAT ION AL
R E CT IF IER
LOGO
ASSEMBLY LOT CODE
OR
IN T E R N AT ION AL
RECTIFIER
LOGO
AS S EM B LY LOT CODE
F 530S
PART NUMB ER
DATE CODE
P = DESIGNATE S LEAD-F RE E
PRODUCT (OPTIONAL)
YEAR 0 = 2000 WEEK 02
A = ASSEMBLY SITE CODE
F530S
PAR T NUMBE R
DATE CODE YE AR 0 = 2000 WEE K 02 LINE L
Page 9
TO-262 Package Outline
Document Number: 91046
www.vishay.com
9
IRF730AS/LPbF
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
TH IS IS AN I RL3103L
E X AMPL E :
LOT CODE 1789 ASS EMBLE D ON WW 19, 1997 IN T HE ASSEMBLY LINE "C"
Note: "P" in ass embl y line pos iti on indicates "L ead-F ree"
INTE RNAT IONAL
RECT IFIER
LOGO
AS S E MB L Y LOT CODE
OR
INTE RNATIONAL
RECT IFIE R
LOGO
ASSEMBLY LOT CODE
PART NUMBE R
DATE CODE YEAR 7 = 1997 WEEK 19 LINE C
PART NUMB ER
DAT E CODE P = DES IGNATES LE AD-F REE
PRODUCT (OPT IONAL)
YEAR 7 = 1997 WE EK 19
A = ASSEMBLY SITE CODE
Page 10
IRF730AS/LPbF
Document Number: 91046
www.vishay.com
10
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
FEED DI RECTION
TRL
FEED DI RECTION
1.85 (.073)
1.65 (.065)
10.90 (.429)
10.70 (.421)
4.10 (.161)
3.90 (.153)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
16.10 (.634)
15.90 (.626)
1.60 (.063)
1.50 (.059)
1.75 (.069)
1.25 (.049)
15.42 (.609)
15.22 (.601)
0.368 (.0145)
0.342 (.0135)
24.30 (.957)
23.90 (.941)
4.72 (.136)
4.52 (.178)
13.50 ( .532)
12.80 ( .504)
330.00 (14.173) MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
27.40 ( 1.079)
23.90 ( .941)
4
26.40 ( 1.03 9)
24.40 ( .961 )
3
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
C
eff. is a fixed capacitance that gives the same charging time
 Starting T
RG = 25Ω, I
I
SD
= 25°C, L = 19mH
J
AS
≤ 5.5A, di/dt ≤ 90A/µs, V
= 5.5A. (See Figure 12)
≤ V
DD
(BR)DSS
,
oss
as C
oss
while V
is rising from 0 to 80% V
DS
Uses IRF730A data and test conditions
TJ ≤ 150°C
* When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
60.00 (2.362) MIN.
30.40 ( 1.197) MAX.
4
DSS
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
03/04
Page 11
Legal Disclaimer Notice
Vishay
Notice
The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of International Rectifier’s Power Control Systems (PCS) business, which closed in April 2007. Specifications of the products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below.
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
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International Rectifier are registered trademarks of International Rectifier Corporation in the U.S. and other countries. All other product names noted herein may be trademarks of their respective owners.
®
, IR®, the IR logo, HEXFET®, HEXSense®, HEXDIP®, DOL®, INTERO®, and POWIRTRAIN
®
Document Number: 99901 www.vishay.com Revision: 12-Mar-07 1
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