l Switch Mode Power Supply (SMPS)
l Uninterruptable Power Supply
l High speed power switching
l Lead-Free
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified (See AN1001)
Absolute Maximum Ratings
ParameterMax.Units
ID @ TC = 25°CContinuous Drain Current, VGS @ 10V5.5
ID @ TC = 100°CContinuous Drain Current, VGS @ 10V3.5A
I
DM
PD @TC = 25°CPower Dissipation74W
V
GS
dv/dtPeak Diode Recovery dv/dt 4.6V/ns
T
J
T
STG
Pulsed Drain Current 22
Linear Derating Factor0.6W/°C
Gate-to-Source Voltage ± 30V
Operating Junction and-55 to + 150
Storage Temperature Range
Soldering Temperature, for 10 seconds300 (1.6mm from case )
Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)
V
DSS
Rds(on) maxI
400V1.0Ω5.5A
SDG
°C
D
Typical SMPS Topologies:
l Single Transistor Flyback Xfmr. Reset
l Single Transistor Forward Xfmr. Reset
Diode Forward Voltage––– –––1.6VTJ = 25°C, IS = 5.5A, VGS = 0V
Reverse Recovery Time––– 370 550nsTJ = 25°C, IF = 3.5A
Reverse RecoveryCharge––– 1.62.4µCdi/dt = 100A/µs
Forward Turn-On TimeIntrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
5.5
22
showing the
A
p-n junction diode.
D
G
S
Page 3
IRF730APbF
Document Number: 91045
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3
100
10
1
0.1
D
I , Drain-to-Source Current (A)
0.01
0.1 1 10 100
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
20µs PULSE WIDTH
T = 25 C
J
V , Drain-to- Source Voltage (V)
DS
4.5V
°
Fig 1. Typical Output Characteristics
100
100
10
1
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
0.1
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
0.01
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
T = 150 C
°
J
Fig 2. Typical Output Characteristics
2.5
I =
D
5.5
5.9A
10
1
D
I , Drain-to-Source Current (A)
0.1
4.05.06.07.08.09.010.0
V , Gate-to-Source Voltage (V)
GS
°
T = 150 C
J
T = 25 C
J
°
V = 50V
20µs PULSE WIDTH
DS
Fig 3. Typical Transfer Characteristics
2.0
1.5
1.0
(Normalized)
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V=
GS
°
10V
Page 4
IRF730APbF
Document Number: 91045
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4
100000
10000
)
F
p
(
e
1000
c
n
a
t
i
c
a
p
a
100
C
,
C
10
100
V
= 0V, f = 1 MHZ
GS
C
= C
C
C
iss
rss
oss
= C
= C
+ Cgd, C
gs
gd
+ C
ds
gd
SHORTED
ds
Ciss
Coss
Crss
1
1101001000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
20
5.5
I =
5.9A
D
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
0
0510152025
Q , Total Gate Charge (nC)
G
V= 320V
DS
V= 200V
DS
V= 80V
DS
FOR TEST CIRCUIT
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
10
1
SD
I , Reverse Drain Current (A)
0.1
0.40.60.81.01.2
T = 150 C
V ,Source-to-Drain Voltage (V)
SD
°
J
°
T = 25 C
J
V = 0 V
GS
Fig 7. Typical Source-Drain Diode
Forward Voltage
10us
10
100us
1ms
1
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 150 C
Single Pulse
0.1
10 100 1000
°
J
V , Drain-to-Source Voltage (V)
DS
10ms
Fig 8. Maximum Safe Operating Area
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IRF730APbF
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5
6.0
5.0
4.0
3.0
2.0
D
I , Drain Current (A)
1.0
0.0
255075100125150
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
R
V
DS
V
GS
R
G
D
D.U.T.
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
+
V
DD
-
thJC
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
Thermal Response (Z )
0.01
0.01
0.000010.00010.0010.010.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T = Px Z+ T
t , Rectangular Pulse Duration (sec)
1
JDMthJCC
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRF730APbF
A
Document Number: 91045
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6
15V
DRIVER
+
-
V
R
20V
V
DS
G
t
L
D.U.T
I
AS
Ω
0.01
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
Q
GD
DD
700
600
TOP
BOTTOM
500
400
300
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
255075100125150
Starting T , Junction Temperature ( C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
610
I
D
2.5A
3.5A
5.5A
°
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
Fig 13b. Gate Charge Test Circuit
)
600
V
(
e
g
590
a
t
l
o
V
580
e
h
c
n
a
l
570
a
v
A
,
v
560
a
S
D
V
550
540
0.01.02.03.04.05.06.0
Fig 12d. Typical Drain-to-Source Voltage
I
, Avalanche Current ( A)
AV
Vs. Avalanche Current
Page 7
IRF730APbF
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7
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P. W .
+
+
V
DD
-
VGS=10V
*
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. ISDWaveform
Body Diode Forward
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
Fig 14. For N-Channel HEXFETS
Current
di/dt
Diode Recovery
dv/dt
V
DD
I
SD
Page 8
IRF730APbF
Document Number: 91045
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8
TO-220AB Package Outline
10.54 (.415)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555 )
13.47 (.530 )
1.40 (.055)
3X
1.15 (.045)
2.54 (.100)
NOTES:
1 DI MENSIONING & TOLERA NCING PER ANSI Y14 .5M, 1982 . 3 OUTLINE CONFORMS TO JEDE C OUTLIN E TO-220AB .
2 CO NTROLLING DIMENSION : INCH 4 HE ATSINK & LEAD MEA SUREMEN TS DO NOT INCLUDE BURRS.
2X
10.29 (.405)
4
1 2 3
3X
3.78 (.149)
3.54 (.139)
- A -
6.47 (.255)
6.10 (.240)
1.15 (.045)
MIN
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.36 ( .014) M B A M
4.69 (.185)
4.20 (.165)
- B -
1.32 (.052)
1.22 (.048)
2.92 (.115)
2.64 (.104)
3X
LEAD ASSIG NMENTS
LEAD ASSIGNMENTS
HEXF ET
1 -GATE2 -DRAIN
1- GA TE
3 -SOURCE
2- DRAIN
3- SOU RCE
4 -DRAIN
4- DRAIN
0.55 (.022)
0.46 (.018)
TO-220AB Part Marking Information
EXAMPLE:
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting T
RG = 25Ω, I
I
SD
TJ ≤ 150°C
J
≤ 5.5A, di/dt ≤ 90A/µs, V
T H IS IS AN IR F 1 0 1 0
LO T COD E 1789
AS S E M B LE D O N W W 19, 1997
IN THE ASSEMBLY LINE "C"
Note: "P" in as sem bly line
position indicates "Lead-Free"
= 25°C, L = 19mH
= 5.5A. (See Figure 12)
AS
DD
≤ V
(BR)DSS
IN T E R N AT IO N AL
RECTIFIER
LOGO
ASS E M B LY
LOT CODE
Pulse width ≤ 300µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
,
oss
while V
is rising from 0 to 80% V
DS
IGBTs, CoPAC K
1- GATE
2- COLLECTO R
3- EMITTER
4- COLLECTO R
PART NUMB ER
DATE CODE
YE AR 7 = 1997
WEEK 19
LINE C
DSS
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
02/04
Page 9
Legal Disclaimer Notice
Vishay
Notice
The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of
International Rectifier’s Power Control Systems (PCS) business, which closed in April 2007. Specifications of the
products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below.
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or
anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
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International Rectifier
are registered trademarks of International Rectifier Corporation in the U.S. and other countries. All other product
names noted herein may be trademarks of their respective owners.
®
, IR®, the IR logo, HEXFET®, HEXSense®, HEXDIP®, DOL®, INTERO®, and POWIRTRAIN