l Application Specific MOSFETs
l Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
l Low Switching Losses
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with Existing Surface Mount Techniques
V
20V
DSS
HEXFET® Power MOSFET
R
DS(on)
5.7mΩ@V
9.7mΩ@V
ST
max
= 10V
GS
= 4.5V
GS
DirectFET ISOMETRIC
Qg(typ.)
11nC
Applicable DirectFET Outline and Substrate Outline (see p.8,9 for details)
SQSXSTMQMXMT
Description
The IRF6623 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to
achieve the lowest on-state resistance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The
DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and
vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power
systems, IMPROVING previous best thermal resistance by 80%.
The IRF6623 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction
and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the
latest generation of processors operating at higher frequencies. The IRF6623 has been optimized for parameters that are
critical in synchronous buck operating from 12 volt buss converters including Rds(on) and gate charge to minimize losses in
the control FET socket.
Absolute Maximum Ratings
Max.
20
±20
55
16
13
120
2.1
1.4
42
43
12
0.017
-40 to + 150
A
W
mJ
A
V
DS
V
GS
@ TC = 25°C
I
D
@ TA = 25°C
I
D
@ TA = 70°C
I
D
I
DM
PD @TA = 25°C
PD @TA = 70°C
@TC = 25°C
P
D
E
AS
I
AR
T
J
T
STG
ParameterUnits
Drain-to-Source VoltageV
Gate-to-Source Voltage
Continuous Drain Current, V
Continuous Drain Current, V
Continuous Drain Current, V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Power Dissipation
Single Pulse Avalanche Energy
Avalanche Current
Linear Derating Factor W/°C
Operating Junction and°C
Storage Temperature Range
Used double sided cooling, mounting pad.
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
T
measured with thermal couple mounted to top (Drain) of
C
part.
R
is measured at T
θ
of approximately 90°C.
J
Conditions
G
2www.irf.com
D
S
Page 3
IRF6623
1000
)
A
(
t
100
n
e
r
r
u
C
e
c
r
10
u
o
S
-
o
t
-
n
i
a
r
1
D
,
D
I
2.5V
≤
60µs PULSE WIDTH
Tj = 25°C
0.1
0.1110100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000.0
)
Α
(
t
n
e
r
r
u
C
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
D
I
100.0
TJ = 150°C
10.0
TJ = 25°C
1.0
V
= 10V
DS
≤
0.1
2.53.03.54.04.55.0
60µs PULSE WIDTH
VGS, Gate-to-Source Voltage (V)
TOP 10V
BOTTOM2.5V
VGS
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
1000
)
A
(
t
n
e
r
r
100
u
C
e
c
r
u
o
S
-
o
t
-
10
n
i
a
r
D
,
D
I
2.5V
≤
60µs PULSE WIDTH
Tj = 150°C
1
0.1110100
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
1.5
e
c
n
a
t
s
i
s
e
R
n
O
)
e
d
c
e
r
z
u
i
l
o
a
S
-
m
r
o
t
o
-
n
N
i
(
a
r
D
,
)
n
o
(
S
D
R
ID = 15A
V
= 10V
GS
1.0
0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
TOP 10V
BOTTOM2.5V
VGS
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
Fig 3. Typical Transfer Characteristics
)
F
p
(
e
c
n
a
t
i
c
a
p
a
C
,
C
10000
1000
100
110100
V
= 0V, f = 1 MHZ
GS
C
= C
C
C
iss
rss
oss
= C
= C
+ Cgd, C
gs
gd
+ C
ds
SHORTED
ds
gd
Ciss
Coss
Crss
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
Fig 4. Normalized On-Resistance vs. Temperature
12
)
ID= 11A
V
10
(
e
g
a
t
l
o
8
V
e
c
r
u
6
o
S
-
o
t
-
e
t
4
a
G
,
S
G
2
V
VDS= 20V
VDS= 10V
0
0102030
Q
Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
www.irf.com3
Page 4
IRF6623
τ
1000.0
)
A
(
t
100.0
n
e
r
r
u
C
n
i
a
r
10.0
D
e
s
r
e
v
e
R
,
1.0
D
S
I
0.1
0.20.40.60.81.01.2
Fig 7. Typical Source-Drain Diode Forward Voltage
TJ = 150°C
TJ = 25°C
V
GS
VSD, Source-to-Drain Voltage (V)
= 0V
1000
OPERATION IN THIS AREA
LIMITED BY RDS(on)
)
A
(
t
100
n
e
r
r
u
C
e
c
r
u
10
o
S
-
o
t
-
n
i
a
r
D
1
,
D
I
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
0110100
V
, Drain-toSource Voltage (V)
DS
Fig 8. Maximum Safe Operating Area
100µsec
1msec
10msec
60
50
)
A
(
40
t
n
e
r
r
u
C
30
n
i
a
r
D
,
20
D
I
10
0
255075100125150
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs. Case Temperature
100
D = 0.50
)
10
A
J
h
t
Z
(
1
e
s
n
o
p
s
e
0.1
R
l
a
m
r
e
h
T
0.01
0.001
1E-0061E-0050.00010.0010.010.1110100
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
t1 , Rectangular Pulse Duration (sec)
τ
J
τ
J
τ
1
τ
1
Ci= τi/Ri
2.5
)
V
(
e
g
a
t
l
o
2.0
V
d
l
o
h
s
e
r
h
t
e
t
a
1.5
G
)
h
t
(
S
G
V
1.0
-75 -50 -250255075 100 125 150
TJ , Temperature ( °C )
Fig 10. Threshold Voltage vs. Temperature
R
R
R
R
1
2
R
1
τ
2
τ
3
R
R
2
3
τ
3
τ
2
3
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
Ri (°C/W) τi (sec)
4
R
4
2.023 0.000678
τ
C
τ
19.48 0.240237
4
τ
4
21.78 2.0167
14.71 58
ID = 250µA
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
4www.irf.com
Page 5
A
)
Ω
20
m
(
e
c
n
a
t
s
i
16
s
e
R
n
O
e
c
r
12
u
o
S
o
t
-
n
i
a
8
r
D
,
)
n
o
(
S
4
D
R
2.04.06.08.010.0
TJ = 125°C
TJ = 25°C
VGS, Gate-to-Source Voltage (V)
ID = 15A
IRF6623
200
)
J
m
(
y
g
160
r
e
n
E
e
h
c
120
n
a
l
a
v
A
e
s
80
l
u
P
e
l
g
n
i
40
S
,
S
A
E
0
255075100125150
Starting TJ, Junction Temperature (°C)
I
TOP
D
5.2A
7.9A
BOTTOM
12A
Fig 12. On-Resistance Vs. Gate Voltage
15V
DRIVER
+
-
V
DD
R
G
V
20V
V
DS
GS
L
D.U.T
I
AS
0.01
t
p
Ω
Fig 13a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 13b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
D.U.T.
+
V
DS
-
Fig 13c. Maximum Avalanche Energy Vs. Drain Current
L
V
DS
D
+
-
V
DD
D.U.T
V
GS
Pulse Widt h < 1µs
Duty Factor < 0.1%
Fig 14a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 14b. Switching Time Waveforms
Vds
Id
Vgs
V
GS
3mA
I
I
Current Sampling Resistors
D
G
Fig 15. Gate Charge Test Circuit
www.irf.com5
Vgs(th)
Qgs1
Qgs2QgdQgodr
Fig 16. Gate Charge Waveform
Page 6
IRF6623
Reverse
Recovery
Current
Driver Gate Drive
P.W.
D.U.T. ISDWaveform
D.U.T. VDSWaveform
Inductor Current
Inductor Curent
* V
GS
D.U.T
+
-
R
G
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-
• di/dt controlled by R
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
+
V
DD
Re-Applied
Voltage
+
-
Period
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P.W.
Period
VGS=10V
V
DD
I
SD
*
Fig 17. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
DirectFET Substrate and PCB Layout, ST Outline
(Small Size Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DirectFET Outline Dimension, ST Outline
(Small Size Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.