l Application Specific MOSFETs
l Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
l Low Switching Losses
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount
V
30V
DSS
R
DS(on)
3.3mΩ
4.4mΩ
max
VGS = 10V
VGS = 4.5V
Qg(typ.)
30nC
Techniques
DirectFET ISOMETRIC
Applicable DirectFET Package/Layout Pad (see p.8,9 for details)
SQSXSTMQ
MX
MT
MX
Description
The IRF6612 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the
lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile. The DirectFET package is compatible with
existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows
dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%.
The IRF6612 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies. The IRF6612 has been optimized for parameters that are critical in synchronous buck converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity to minimize losses in the synchronous FET socke
t.
ute Maximum Ratings
ParameterUnits
V
DS
V
GS
@ TC = 25°C
I
D
@ TA = 25°C
I
D
@ TA = 70°C
I
D
I
DM
PD @TA = 25°CPower Dissi pation
PD @TA = 70°C
@TC = 25°CPower Dissipation
P
D
T
J
T
STG
erma
Drain-to-Sour ce Voltage
Gate-to-Source Volt age
Conti n uous Drai n Cur r e nt, V
Conti n uous Drai n Cur r e nt, V
Conti n uous Drai n Cur r e nt, V
Pulsed Drain Current
Power Dissipation
Linear D er ating Factor
Operating Junction and
Stor ag e Temperat ur e Ra ng e
cgg
stance
ParameterTyp.Max.Units
R
θJA
R
θJA
R
θJA
R
θJC
R
θJ-PCB
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
Junction-to-PCB M ou nted1.0–––
fjgjhj
ij
Notes through are on page 10
@ 10V
GS
@ 10V
GS
@ 10V
GS
–––45
12.5–––
–––1.4
Max.
30
±20
136
24
19
190
2.8
1.8
89
0.022
-40 to + 150
20–––°C/W
V
A
W
W/°C
°C
www.irf.com1
02/02/04
Page 2
IRF6612/IRF6612TR1
Static @ TJ = 25°C (unless o therwi se specified)
ParameterMin. Typ. Max. Units
BV
DSS
∆Β
V
DSS
R
DS(on)
V
GS(th)
∆
V
GS(th)
I
DSS
I
GSS
gfsForwa rd Tr a nsconductanc e96– –––––S
Q
g
Q
gs1
Q
gs2
Q
gd
Q
godr
Q
sw
Q
oss
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Avalanche Characteristics
E
AS
I
AR
Diode Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
/∆T
/∆T
Drain-t o-Source Breakdown Voltage30––––––V
Breakdown Vol t age Temp. Co ef f icient –––24––– mV/°C
J
Static Drai n-to-Sou rce On-Res istance –––2.53.3
–––3.44.4
Gate Threshold Voltage1.35–––2.25V
Gate Threshold Voltage Coeffici ent–––-5.6––– mV/°C
Total Gat e Charge –––3045
Pre-Vth Gate-to-Source Char ge–––8.5–– –
Post-Vth Gate-to-Source Charge–––2.9–––nC
Gate -t o - D rain Charge–––10–––
Gate Charge Overdrive–––8.6–––
Switch Charge (Q
gs2
+ Qgd)
–––13–––
Output Charge–––18–––nC
Turn- On D el ay Time–––15–––
Rise Time–––52–––
Turn-O ff Delay Ti m e–––21–––ns
Fall Time–––4.8–––
Input Capacitance–––3970–––
Output Capacitance–––780–––pF
Reverse Transfer Cap acitance–––360–––
ParameterUnits
Single Pulse Avalanche En er gy
Avalanche Current
c
d
Typ.
–––
–––
ParameterMin. Typ. Max. Units
Conti n uous Source Curren t ––––––24
(Body Diode)A
Pulsed Source Curren t––––––190
(Body Diode)
Diode Forward Voltage––––––1.0V
Reverse Reco very Time–––1929ns
Reverse Recovery Charge–––8.112nC
c
Conditions
VGS = 0V, ID = 250µA
Referen c e to 25° C, I
V
mΩ
= 10V, ID = 24A
GS
VGS = 4.5V, ID = 19A
VDS = VGS, ID = 250µA
V
= 24V, VGS = 0V
DS
= 24V, VGS = 0V, TJ = 125°C
V
DS
V
= 20V
GS
V
= -20V
GS
= 15V, ID = 19A
V
DS
VDS = 15V
= 4.5V
V
GS
I
= 19A
D
= 16V, VGS = 0V
V
DS
V
= 16V, VGS = 4.5V
DD
= 19A
I
D
Clampe d I n ductiv e Load
V
= 0V
GS
= 15V
V
DS
ƒ = 1.0MHz
Max.
37
19
Conditions
MOSFET symbol
showing the
integral reverse
p-n junct ion diode.
TJ = 25°C, IS = 19A, VGS = 0V
T
= 25°C, IF = 19A
J
di/dt = 100A/µs
e
= 1mA
D
e
e
e
G
mJ
A
D
S
e
2www.irf.com
Page 3
IRF6612/IRF6612TR1
10000
VGS
7.0V
4.5V
4.0V
3.5V
3.2V
2.9V
2.7V
60µs PULSE WIDTH
≤
Tj = 25°C
)
A
(
t
n
e
r
r
u
C
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
D
I
TOP 10V
1000
BOTTOM2.7V
100
10
1
0.1110
VDS, Drain-to-Source Voltage (V )
Fig 1. Typical Output Characteristics
1000
)
A
(
t
n
e
r
100
r
u
C
e
c
r
u
o
S
-
o
t
-
10
n
i
a
r
D
,
D
I
TOP 10V
BOTTOM2.7V
VGS
7.0V
4.5V
4.0V
3.5V
3.2V
2.9V
2.7V
60µs PULSE WIDTH
≤
Tj = 150°C
1
0.1110
VDS, Drain-to-Source Voltage (V )
Fig 2. Typical Output Characteristics
1000
V
= 10V
DS
≤
)
Α
(
100
t
n
e
r
r
u
C
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
D
I
60µs PULSE WIDTH
10
1
TJ = 150°C
TJ = 25°C
0.1
012345
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
1.5
e
c
n
a
t
s
i
s
e
R
n
O
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
)
n
o
(
S
D
R
ID = 25A
V
= 10V
GS
)
d
e
z
i
l
1.0
a
m
r
o
N
(
0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
www.irf.com3
Page 4
IRF6612/IRF6612TR1
100000
)
F
10000
p
(
e
c
n
a
t
i
c
a
p
a
C
,
1000
C
100
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
+ Cgd, C
gs
gd
+ C
ds
ds
gd
iss
C
rss
C
oss
C
iss
C
oss
C
rss
110100
VDS, Drain-to-Source Voltage (V )
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
SHORTED
6.0
ID= 19A
)
5.0
V
(
e
g
a
t
l
4.0
o
V
e
c
r
u
3.0
o
S
-
o
t
-
e
t
2.0
a
G
,
S
G
1.0
V
0.0
0 10203040
Q
VDS= 24V
VDS= 15V
Total G ate Charge (nC)
G
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
1000.00
)
A
(
t
n
e
r
r
100.00
u
C
n
i
a
r
D
e
s
r
e
v
10.00
e
R
,
D
S
I
1.00
TJ = 150°C
TJ = 25°C
V
= 0V
GS
0.40.50.60.70.80.91.01.1
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
1000
OPERATION IN THIS AREA
)
A
(
t
100
n
e
r
r
u
C
e
c
r
u
10
o
S
-
o
t
-
n
i
a
r
D
1
,
TA = 25°C
D
I
Tj = 150°C
Single Pulse
0.1
01101001000
LIMITED BY RDS(on)
100µsec
1msec
10msec
VDS, Drain-to-Source Voltage (V )
Fig 8. Maximum Safe Operating Area
Forward Voltage
4www.irf.com
Page 5
IRF6612/IRF6612TR1
τ
140
120
)
100
A
(
t
n
e
r
80
r
u
C
n
i
60
a
r
D
,
D
40
I
20
0
255075100125150
TC , Case Temper ature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
2.5
)
V
(
2.0
e
g
a
t
l
o
V
d
l
1.5
o
h
s
e
r
h
t
1.0
e
t
a
G
)
h
t
(
0.5
S
G
V
0.0
-75 -50 -250255075 100 125 150
ID = 250µA
TJ , Temperature ( °C )
Fig 10. Threshold Voltage vs. Temperature
100
D = 0.50
)
10
A
J
h
t
Z
(
1
e
s
n
o
p
s
e
0.1
R
l
a
m
r
e
h
T
0.01
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
( THER M A L R ESPO N SE )
τ
J
τ
J
τ
1
τ
1
Ci= τi/Ri
R
R
R
R
1
2
R
1
τ
2
τ
3
R
R
2
3
τ
3
τ
2
3
Ri (°C/W) τi (sec)
4
R
4
1.2801 0.000322
τ
C
τ
8.7256 0.164798
4
τ
4
21.750 2.25760
13.251 69
Notes:
1. Du t y Fact o r D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
0.001
1E-0061E-0050.00010.0010.010.1110100
t1 , Rectangular Pulse Dur ation (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
www.irf.com5
Page 6
IRF6612/IRF6612TR1
)
10
Ω
m
(
9
e
c
n
8
a
t
s
i
s
7
e
R
n
6
O
e
c
r
5
u
o
S
4
o
t
-
n
3
i
a
r
D
2
,
)
n
o
1
(
S
D
0
R
TJ = 25°C
ID = 24A
TJ = 125°C
2345678910
V
Gate -to - Source Volt age (V)
GS,
Fig 12. On-Resistance vs. Gate Voltage
15V
V
R
G
20V
VGS
L
DS
D.U.T
I
AS
Ω
0.01
t
p
DRIVER
+
V
DD
-
A
I
AS
t
150
)
J
m
(
y
125
g
r
e
n
E
e
100
h
c
n
a
l
a
v
75
A
e
s
l
u
P
50
e
l
g
n
i
S
25
,
S
A
E
0
255075100125150
TOP 5.3A
BOTTOM19A
I
D
6.2A
Starting TJ , Junction Temperature (°C)
Fig 13. Maximum Avalanche Energy
vs. Drain Current
Current Regulator
V
(BR)DSS
p
Same Type as D.U.T.
.2µF
12V
V
GS
50KΩ
3mA
.3µF
D.U.T.
+
V
DS
-
I
G
D
Fig 14. Unclamped Inductive Test Circuit
I
Current Sampling Resistors
and Waveform
Fig 15. Gate Charge Test Circuit
L
D.U.T
D
V
DS
+
-
V
DD
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 17. Switching Time Waveforms
V
DS
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 16. Switching Time Test Circuit
6www.irf.com
Page 7
IRF6612/IRF6612TR1
Reverse
Recovery
Current
Driver Gate Drive
P.W.
D.U.T. ISDWaveform
D.U.T. VDSWaveform
Inductor Curent
* V
GS
D.U.T
+
-
R
G
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-
• dv/dt controlled by R
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
+
V
DD
Re-Applied
Voltage
+
-
Period
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P.W.
Period
VGS=10V
V
DD
I
SD
*
Fig 15.Peak Diode Recovery dv/dt Test Circuit for N-Channel
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.