l Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
l Low Switching Losses
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount Techniques
Applicable DirectFET Outline and Substrate Outline (see p.7, 8 for details)
SQSXSTMQMXMT
V
30V
DSS
Description
The IRF6608 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to
achieve the lowest on-state resistance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The DirectFET
package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase,
infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and
processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous
best thermal resistance by 80%.
The IRF6608 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest
generation of processors operating at higher frequencies. The IRF6608 has been optimized for parameters that are critical in
synchronous buck converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6608 has been
optimized for parameters that are critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in
the control FET socket.
R
DS(on)
9.0mΩ@V
max
= 10V
GS
11mΩ@VGS = 4.5V
ST
DirectFET ISOMETRIC
Qg
16nC
Absolute Maximum Ratings
ParameterUnits
V
DS
V
GS
@ TC = 25°C
I
D
I
@ TA = 25°C
D
@ TA = 70°C
I
D
I
DM
P
@TA = 25°C
D
P
@TA = 70°C
D
P
@TC = 25°C
D
T
J
T
STG
Drain-to-Source VoltageV
Gate-to-Source Voltage
Continuous Drain Current, V
Continuous Drain Current, V
Continuous Drain Current, V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Power Dissipation
Linear Derating Factor W/°C
Operating Junction and°C
Storage Temperature Range
Total Gate Charge –––1624
Pre-Vth Gat e -t o-S ou r ce Char ge–––4.6–––
Post-Vth Gate-to-Source Charge–––1.4–––nC
Gate-to-Drain Charge–––5.3–––
Gate Charge Overdrive–––4.7–––See Fig. 16
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
T
measured with thermal couple mounted to top (Drain) of part.
C
R
is measured at T
θ
MOSFET symbol
showing the
integral reverse
p-n junction diode.
T
= 25°C, IS = 8.8A, VGS = 0V e
J
= 25°C, IF = 8.8A
T
J
di/dt = 100A/µs e
of approximately 90°C.
J
2www.irf.com
Conditions
G
mJ
A
mJ
D
S
Page 3
IRF6608
100
)
A
(
t
n
e
r
r
u
C
e
c
r
10
u
o
S
-
o
t
-
n
i
a
r
D
,
D
I
2.7V
TOP 10V
BOTTOM 2.7V
30µs PULSE WIDTH
Tj = 25°C
1
0.11.010.0100.0
Fig 1. Typical Output Characteristics
100.0
)
Α
(
t
n
e
r
r
u
C
e
c
r
10.0
u
o
S
-
o
t
-
n
i
a
r
D
,
D
I
1.0
2.52.83.03.33.5
TJ = 150°C
TJ = 25°C
V
= 20V
DS
30µs PULSE WIDTH
VGS, Gate-to-Source Voltage (V)
VGS
7.0V
4.5V
3.8V
3.5V
3.2V
2.9V
100
)
A
(
t
n
e
r
r
u
C
e
c
r
10
u
o
S
-
o
t
-
n
i
a
r
D
,
D
I
1
TOP 10V
BOTTOM 2.7V
2.7V
VGS
7.0V
4.5V
3.8V
3.5V
3.2V
30µs PULSE WIDTH
2.9V
Tj = 150°C
0.11.010.0100.0
Fig 2. Typical Output Characteristics
2.0
e
c
n
a
t
s
i
s
e
R
n
O
)
e
d
c
e
r
z
u
i
l
o
a
S
-
m
o
r
t
o
-
n
N
i
(
a
r
D
,
)
n
o
(
S
D
R
ID = 12A
V
= 10V
GS
1.5
1.0
0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
)
F
p
(
e
c
n
a
t
i
c
a
p
a
C
,
C
10000
1000
100
110100
V
= 0V, f = 1 MHZ
GS
C
= C
C
C
iss
rss
oss
= C
= C
+ Cgd, C
gs
gd
+ C
ds
SHORTED
ds
gd
Ciss
Coss
Crss
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
Fig 4. Normalized On-Resistance vs. Temperature
12
)
ID= 8.8A
V
10
(
e
g
a
t
l
o
8
V
e
c
r
u
6
o
S
-
o
t
-
e
t
4
a
G
,
S
G
2
V
VDS= 24V
VDS= 15V
0
010203040
Q
Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
www.irf.com3
Page 4
IRF6608
τ
100.0
)
A
(
t
n
e
r
r
10.0
u
C
n
i
a
r
D
e
s
r
e
v
1.0
e
R
,
D
S
I
TJ = 150°C
TJ = 25°C
V
GS
= 0V
0.1
0.20.40.60.81.01.2
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
60
50
)
A
(
40
t
n
e
r
r
u
C
30
n
i
a
r
D
,
20
D
I
10
)
V
(
e
g
a
t
l
o
V
d
l
o
h
s
e
r
h
t
e
t
a
G
V
1000
OPERATION IN THIS AREA
LIMITED BY RDS(on)
)
A
(
t
100
n
e
r
r
u
C
e
c
r
u
10
o
S
-
o
t
-
n
i
a
r
D
1
,
D
I
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
01101001000
V
, Drain-toSource Voltage (V)
DS
Fig 8. Maximum Safe Operating Area
2.2
2.0
1.8
1.6
1.4
1.2
)
h
t
(
S
G
1.0
100µsec
1msec
10msec
ID = 250µA
0
255075100125150
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs. Case Temperature
100
D = 0.50
)
10
A
J
h
t
Z
(
1
e
s
n
o
p
s
e
0.1
R
l
a
m
r
e
h
T
0.01
0.001
1E-0061E-0050.00010.0010.010.1110100
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
t1 , Rectangular Pulse Duration (sec)
τ
J
τ
J
τ
1
τ
1
Ci= τi/Ri
0.8
-75 -50 -250255075 100 125 150
TJ , Temperature ( °C )
Fig 10. Threshold Voltage vs. Temperature
R
R
R
R
1
2
R
1
τ
2
3
R
R
2
3
τ
3
τ
τ
2
3
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
Ri (°C/W) τi (sec)
4
R
4
2.023 0.000678
τ
C
τ
19.48 0.240237
4
τ
4
21.78 2.0167
14.71 58
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
4www.irf.com
Page 5
IRF6608
A
)
0.025
Ω
(
e
c
n
a
t
s
i
s
0.020
e
R
n
O
e
c
r
u
0.015
o
S
o
t
-
n
i
a
r
0.010
D
,
)
n
o
(
S
D
0.005
R
345678910
V
Gate -to -Source Voltage (V)
GS,
ID = 12A
Fig 12. On-Resistance Vs. Gate Voltage
15V
DRIVER
+
-
V
R
V
20V
V
DS
G
GS
L
D.U.T
I
AS
0.01
t
p
Ω
Fig 13a. Unclamped Inductive Test Circuit
DD
240
)
J
m
(
y
200
g
r
e
n
E
e
160
h
c
n
a
l
a
120
v
A
e
s
l
u
80
P
e
l
g
n
i
S
40
,
S
A
E
0
255075100125150
I
TOP
D
3.3A
3.8A
BOTTOM
8.8A
Starting TJ, Junction Temperature (°C)
Fig 13c. Maximum Avalanche Energy Vs. Drain Current
L
D.U.T
D
+
-
V
DD
V
DS
V
GS
Pulse Widt h < 1µs
Duty Factor < 0.1%
V
(BR)DSS
t
p
I
AS
Fig 13b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
Fig 14a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 14b. Switching Time Waveforms
Vds
Vgs(th)
Qgs1
Qgs2QgdQgodr
Id
Vgs
Fig 15. Gate Charge Test Circuit
www.irf.com5
Fig 16. Gate Charge Waveform
Page 6
IRF6608
Reverse
Recovery
Current
Driver Gate Drive
P.W.
D.U.T. ISDWaveform
D.U.T. VDSWaveform
Inductor Current
Inductor Curent
* V
GS
D.U.T
+
-
R
G
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-
• di/dt controlled by R
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
+
V
DD
Re-Applied
Voltage
+
-
Period
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P.W.
Period
VGS=10V
V
DD
I
SD
*
Fig 17. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
DirectFET Substrate and PCB Layout, ST Outline
(Small Size Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.