Datasheet irf6607 Datasheet

PD - 94574

IRF6607

HEXFET® Power MOSFET

V

l Application Specific MOSFETs l Ideal for CPU Core DC-DC Converters l Low Conduction Losses l High Cdv/dt Immunity l Low Profile (<0.7 mm) l Dual Sided Cooling Compatible l Compatible with existing Surface

DSS

30V

Mount Techniques

Description

The IRF6607 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the lowest on-state resistance in a package that has the footprint of an SO-8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%.

The IRF6607 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors operating at higher frequencies. The IRF6607 has been optimized for parameters that are critical in synchronous buck converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6607 offers particularly low Rds(on) and high Cdv/dt immunity for synchronous FET applications.

Absolute Maximum Ratings

Parameter Units

V

DS

V

GS

@ TC = 25°C

I

D

@ TA = 25°C

I

D

@ TA = 70°C

I

D

I

DM

PD @TA = 25°C

PD @TA = 70°C

@TC = 25°C

P

D

T

J

T

STG

Drain-to-Source Voltage V

Gate-to-Source Voltage

Continuous Drain Current, V

Pulsed Drain Current

Power Dissipation

Linear Derating Factor W/°C Operating Junction and °C

Storage Temperature Range

c g g

@ 10V

GS

@ 10V

GS

@ 10V

GS

-40 to + 150

3.3mΩ@V

4.4mΩ@V

Max.

30

±12

94

27

22

220

3.6

2.3

42

0.029

R

DS(on)

max

= 10V

GS

= 4.5V

GS

DirectFET ISOMETRIC

Qg

50nC

A

W

Thermal Resistance

Parameter Typ. Max. Units

R

θJA

R

θJA

R

θJA

R

θJC

R

θJ-PCB

Junct ion-to-Ambient

Junct ion-to-Case

Junction-to-PCB Mounted ––– 1.0

f g h

i

––– 35

12.5 –––

20 ––– °C/W

––– 3.0

Notes  through  are on page 11

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10/24/02

IRF6607

/

gy

(

)

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

BV

DSS

∆Β

V

DSS

R

DS(on)

V

GS(th)

∆

V

GS(th)

I

DSS

I

GSS

gfs Forward Transconductance 120 ––– ––– S

Q

g

Q

gs1

Q

gs2

Q

gd

Q

godr

Q

sw

Q

oss

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

Drain-to-Source Breakdown Voltage 30 ––– ––– V

∆

T

Breakdown Voltage Temp. Coefficient ––– 29 ––– mV/°C

J

Static Drain-to-Source On-Resistance ––– 2.5 3.3

––– 3.4 4.4

Gate Threshold Voltage 1.0 ––– ––– V

∆

T

Gate Threshold Voltage Coefficient ––– -5.3 ––– mV/°C

J

Drain-to-Source Leakage Current ––– ––– 30 µA

––– ––– 100

Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

Total Gate Charge ––– 50 75

Pre-Vth Gate-to-Source Charge ––– 13 –––

Post-Vth Gate-to-Source Charge ––– 4.0 ––– nC

Gate-to-Drain Charge ––– 16 –––

Gate Charge Overdrive ––– 18 ––– See Fig. 16 Switch Charge (Q

gs2

+ Qgd)

–––20–––

Output Charge ––– 30 ––– nC

Turn-On Delay Time ––– 60 –––

Rise Time ––– 8.0 –––

Turn-Off Delay Time ––– 32 ––– ns

Fall Time –––13–––

Input Capacitance ––– 6930 –––

Output Capacitance ––– 1260 ––– pF

Reverse Transf er Capacitance ––– 510 –––

VGS = 0V, ID = 250µA

Reference to 25°C, I

mΩ

V

GS

V

GS

VDS = VGS, ID = 250µA

V

DS

VDS = 24V, VGS = 0V, TJ = 70°C

V

GS

V

GS

V

DS

V

DS

V

GS

I

= 20A

D

V

DS

V

DD

I

= 20A

D

Clamped Inductive Load

V

GS

V

DS

ƒ = 1.0MHz

Avalanche Characteristics

Parameter Units

E

AS

I

AR

E

AR

Single Pulse Avalanche Ener

Avalanche Current

c

Repetitive Avalanche Energy

d

c

Typ.

–––

Diode Characteristics

Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Continuous Source Current ––– ––– 27

(Body Diode) A Pulsed Source Current ––– ––– 220

Body Diode

c

Diode Forward Voltage ––– 1.0 1.3 V

Reverse Recovery Time ––– 46 69 ns

Reverse Recovery Charge ––– 54 81 nC

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

MOSFET symbol

showing the integral reverse

p-n junction diode. TJ = 25°C, IS = 20A, VGS = 0V

T

= 25°C, IF = 20A

J

di/dt = 100A/µs

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Conditions

= 10V, ID = 25A

= 4.5V, ID = 20A

= 24V, VGS = 0V

= 12V

= -12V

= 15V, ID = 20A

= 15V

= 4.5V

= 16V, VGS = 0V

= 15V, VGS = 4.5V

= 0V

= 15V

Max.

51

20

0.36

Conditions

e

= 1mA

D

e

e

G

mJ

A

D

S

e

IRF6607

1000

)

100

A

( t n e

r

r u

C

10

e c

r u o S

-

1

o

t

n

i a

r D

,

0.1

D

I

2.0V

20µs PULSE WIDTH Tj = 25°C

0.01

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

1000.00

TOP 12V

BOTTOM 2.0V

VGS

10V

4.5V

3.0V

2.7V

2.5V

2.2V

1000

TOP 12V

) A

( t n e

r

100

r u

C e

c

r u o S

o

t

n

10

i a

r D

,

D

I

2.0V

20µs PULSE WIDTH

BOTTOM 2.0V

Tj = 150°C

1

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

2.0

I =

D

25A

VGS

10V

4.5V

3.0V

2.7V

2.5V

2.2V

)

Α

(

t

100.00

n e

r

r u

C e

c

r

10.00

u o S

o

t

n

i a

r

1.00

D ,

D

I

0.10

Fig 3. Typical Transfer Characteristics

TJ = 150°C

TJ = 25°C

V

= 15V

DS

20µs PULSE WIDTH

2.0 2.5 3.0 3.5 4.0

VGS, Gate-to-Source Voltage (V)

1.5

1.0

(Normalized)

0.5

DS(on)

R , Drain-to-Source On Resistance

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ, Junction Temperature (°C)

Fig 4. Normalized On-Resistance

V =

GS

10V

vs. Temperature

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IRF6607

100000

) F

10000

p

( e c n a

t

i c a p a

C ,

1000

C

100

V

= 0V, f = 1 MHZ

GS

C

= C

+ Cgd, C

gs

gd

+ C

ds

iss

C

rss

C

oss

C

iss

C

oss

C

rss

1 10 100

VDS, Drain-to-Source Voltage (V)

SHORTED

ds

gd

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000.00

) A

( t

100.00

n e

r

r u

C n

i a

r D e

s

r e v e

R ,

D S

I

10.00

1.00

0.10

TJ = 150°C

TJ = 25°C

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

VSD, Source-to-Drain Voltage (V)

V

GS

= 0V

) V

( e

g a

t

l o V

e c

r u o S

o

t

e

t a

G ,

V

6.0 ID= 20A

5.0

4.0

3.0

2.0

S G

1.0

0.0

0 102030405060

Q

G

VDS= 24V

VDS= 15V

Total Gate Charge (nC)

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

) A

( t

100

n e

r

r u

C e

c

r

10

u o S

o

t

n

i a

r

1

D ,

D

I

0.1 0 1 10 100 1000

OPERATION IN THIS AREA LIMITED BY RDS(on)

100µsec

1msec

10msec

TA = 25°C

Tj = 150°C Single Pulse

VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

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IRF6607

30

25

20

15

10

D

I , Drain Current (A)

5

0

25 50 75 100 125 150

TA, Ambient Temperature (°C)

Fig 9. Maximum Drain Current Vs.

Ambient Temperature

100

2.0

) V

( e

g a

t

l o

1.5

V d

l o h s e

r h

t e

t a

1.0

G

) h

t

( S G

V

0.5

-75 -50 -25 0 25 50 75 100 125 150

ID = 250µA

TJ , Temperature ( °C )

Fig 10. Threshold Voltage Vs. Temperature

D = 0.50

10

thJA

Thermal Response (Z )

0.20

0.10

0.05

1

0.02

0.01

SINGLE PULSE

0.1

0.01

0.00001 0.0001 0.001 0.01 0.1 1 10 100

(THERMAL RESPONSE)

t , Rectangular Pulse Duration (sec)

1

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

J DM thJA A

1 2

P

DM

t

1

t

2

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF6607

A

15V

DRIVER

+

V

DD

-

R

V

20V

V

DS

G

GS

L

D.U.T

I

AS

Ω

0.01

t

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

I

AS

Fig 12b. Unclamped Inductive Waveforms

120

TOP

100

80

60

40

20

AS

E , Single Pulse Avalanche Energy (mJ)

0

25 50 75 100 125 150

BOTTO M

Starting TJ, Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

L

V

DS

D

I

D

8.9A

16A

20A

V

DD

Current Regulator

Same Type as D.U.T.

12V

.2µF

V

GS

50KΩ

3mA

.3µF

D.U.T.

V

GS

Pulse Width < 1µs

Duty Factor < 0.1%

Fig 14a. Switching Time Test Circuit

+

V

DS

-

V

DS

90%

D.U.T

10%

I

G

Current Sampling Resistors

I

D

Fig 13. Gate Charge Test Circuit

V

GS

t

d(on)tr

t

d(off)tf

Fig 14b. Switching Time Waveforms

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IRF6607

+

-

Reverse Recovery Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

D.U.T

+



-

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

+



V

DD

R

G

• dv/dt controlled by R

• Driver same type as D.U.T.

• I

controlled by Duty Factor "D"

SD

• D.U.T. - Device Under Test

G

Re-Applied Voltage

Inductor Curent

* V

GS

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

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IRF6607

)

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R MOSFET, but these conduction losses are only about one half of the total losses.

Power losses in the control switch Q1 are given by;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

= I

()

rms

 

+ I ×



+ Q

()

g

Q



+



This simplified loss equation includes the terms Q and Q

charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q Fig 16.

the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I gins to change. Minimizing Q reducing switching losses in Q1.

put capacitance of the MOSFET during every switching cycle. Figure A shows how Q parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.

which are new to Power MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the out-

oss

2

Q

× R

gd

i

g

+ P

ds(on )

× Vin× f

switching

 



+ P

 

+ I ×



drive

Q

+ P

gs 2

i

g

× Vg× f

oss

2

dmax

×Vin× f

 

and Q

gs1

at which time the drain voltage be-

, can be seen from

gs2

is a critical factor in

gs2

is formed by the

oss

of the

ds(on)

output

× Vin× f

Synchronous FET

The power loss equation for Q2 is approximated

by;

P

= P

loss

P

loss

+ Qg× Vg× f

+

conduction

= I

rms

()



Q

 

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R

portant characteristic; however, once again the im-

 

portance of gate charge must not be overlooked since



it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q verse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

gs2

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Q potential for Cdv/dt turn on.

Figure A: Q

+ P

2

× R

ds(on)()

oss

×Vin× f

2

must be minimized to reduce the

gs1

Characteristic

oss

drive

*

+ P

output



+ Qrr× Vin× f

(



ds(on)

oss

is an im-

and re-

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DirectFET Outline Dimension

IRF6607

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IRF6607

DirectFET PCB Footprint

DirectFET

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Tape and Reel Dimension

DirectFET Part Marking

IRF6607

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature.

 Starting T

RG = 25Ω, I

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

= 25°C, L = 0.25mH

J

= 20A.

AS

This product has been designed and qualified for the Consumer market.

 Surface mounted on 1 in. square Cu board.  Used double sided cooling , mounting pad.  Mounted on minimum footprint full size board with metalized

back and with small clip heatsink.

 T

measured with thermal couple mounted to top (Drain) of

C

part.

Data and specifications subject to change without notice.

Qualification Standards can be found on IR’s Web site.

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.10/02

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