This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy inthe breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17423.
Ordering Information
P AR T NUMBERP ACKAGEBRAND
IRF646TO-220ABIRF646
NOTE: When ordering, use the entire part number.
File Number
Features
• 14A, 275V
•r
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• 275VDC Rating-120VAC Line System Operation
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
= 0.280Ω
DS(ON)
Components to PC Boards”
Symbol
D
2169.3
Packaging
G
S
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
4-214
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
550mJ
-55 to 150
300
260
o
C
o
C
o
C
NOTE:
1. TJ= 25oC to 125oC
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAX UNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
On-State Drain Current (Note 2)I
D(ON)VDS
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 2)r
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
2.5
2.0
1.5
1.0
, DRAIN TO SOURCE
ON RESISTANCE (Ω)
0.5
DS(ON)
r
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
15
ID, DRAIN CURRENT (A)
30
VGS = 10V
4560
= 20V
V
GS
75
3.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
= 10V, ID = 14A
V
GS
2.4
1.8
1.2
ON RESISTANCE
0.6
NORMALIZED DRAIN TO SOURCE
0
-60 -40 -2002040 60
, JUNCTION TEMPERATURE (oC)
T
J
80
100
120 140 160
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4-217
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Page 5
IRF646
Typical Performance Curves
1.25
ID = 250µA
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-60 -40 -20020 40 60
, JUNCTION TEMPERATURE (oC)
T
J
Unless Otherwise Specified (Continued)
80
100 120 140 160
FIGURE 10. NORMALIZED DRAIN TOSOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
15
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
≥ 50V
V
DS
12
9
25oC
150oC
3000
2400
1800
1200
C, CAPACITANCE (pF)
600
0
0
VGS= 0V, f = 1MHz
, DRAIN TO SOURCE VOLTAGE (V)
V
DS
10
C
= CGS + C
ISS
C
= C
RSS
C
≈ C
OSS
C
ISS
C
OSS
C
RSS
GD
DS
+ C
GD
GD
100
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
10
6
, TRANSCONDUCTANCE (S)
3
fs
g
0
05101520
I
, DRAIN CURRENT (A)
D
1
, SOURCE TO DRAIN CURRENT (A)
SD
I
25
0.1
150oC
0
VSD, SOURCE TO DRAIN VOLTAGE (V)
25oC
0.81.21.62.00.4
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE FORWARD VOLTAGE
20
ID = 14A
16
12
8
, GATE TO SOURCE (V)
GS
4
V
0
012243648
, GATE CHARGE (nC)
Q
g
VDS = 125V
VDS = 50V
VDS = 200V
60
4-218
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Page 6
IRF646
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
+
V
DD
-
DUT
0V
P
I
AS
0.01Ω
0
t
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
P
I
AS
t
AV
V
DS
V
DD
t
ON
t
d(ON)
t
R
L
+
V
R
G
DD
-
V
DS
90%
0
r
10%
DUT
V
GS
V
GS
10%
0
50%
PULSE WIDTH
FIGURE 17. SWITCHING TIME TEST CIRCUITFIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
12V
BATTERY
0
0.2µF
50kΩ
I
G(REF)
CURRENT
REGULATOR
0.3µF
G
IG CURRENT
SAMPLING
RESISTORRESISTOR
SAME TYPE
AS DUT
D
DUT
S
CURRENT
I
D
SAMPLING
(ISOLATED
SUPPLY)
V
DS
V
DD
Q
g(TOT)
Q
gd
Q
gs
V
DS
0
I
G(REF)
0
t
d(OFF)
90%
V
GS
t
OFF
50%
t
f
10%
90%
FIGURE 19. GATE CHARGE TEST CIRCUITFIGURE 20. GATE CHARGE WAVEFORMS
4-219
Page 7
IRF646
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly , the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
4-220
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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