This is an N-Channel enhancement mode silicon gate power
field effect transistor. It is an advanced power MOSFET
designed, tested, and guaranteed to withstand a specified
level of energy in the breakdown avalanche mode of operation. This power MOSFET is designed for applications such
as switching regulators, switching converters, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.
Formerly developmental type TA17443.
Symbol
D
G
S
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . .T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
61mJ
-55 to 150
300
260
o
C
o
C
o
C
NOTE:
1. TJ= 25oC to 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAX UNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
On-State Drain Current (Note 2)I
D(ON)VDS
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 2)r
DS(ON)VGS
Forward Transconductance (Note 2)g
Turn-On Delay Timet
d(ON)
Rise Timet
Turn-Off Delay Timet
d(OFF)
Fall Timet
Total Gate Charge
Q
g(TOT)VGS
(Gate to Source + Gate to Drain)
Gate to Source ChargeQ
Gate to Drain “Miller” ChargeQ
Input CapacitanceC
Output CapacitanceC
Reverse Transfer CapacitanceC
DSSVGS
DSS
GSS
fs
r
f
gs
gd
ISS
OSS
RSS
= 0V, ID = 250µA, (Figure 10)250--V
= VDS, ID = 250µA2.0-4.0V
VDS = Rated BV
VDS = 0.8 x Rated BV
, VGS = 0V--25µA
DSS
, VGS = 0V
DSS
--250µA
TJ = 125oC
> I
D(ON)
x r
DS(ON)MAX
, VGS = 10V,
2.0--A
(Figure 7)
VGS = ±20V--±100nA
= 10V, ID = 2.5A, (Figures 8, 9)-1.62.0A
VDS > I
D(ON)
x r
DS(ON)MAX
, ID = 2.5A,
0.81.2-S
(Figure 12)
VDD = 0.5 x Raterd BV
, ID≈ 2.0A, RL = 61Ω
DSS
-8.913ns
VGS = 10V, (Figures 17, 18)
MOSFET Switching Times are Essentially Independent of Operating Temperature
-1218ns
-1827ns
-8.915ns
= 10V, ID = 2.0A, VDS = 0.8 x Rated BV
I
= 1.5mA (Figures 14, 19, 20) Gate
G(REF)
DSS
-9.614.4nC
Charge is Essentially Independent of Operating
Temperature
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
4
Page 5
IRF614
Typical Performance Curves
10
8
6
4
, DRAIN TO SOURCE
ON RESISTANCE (Ω)
2
DS(ON)
r
0
0
2
4
ID, DRAIN CURRENT (A)
Unless Otherwise Specified (Continued)
VGS = 10V
VGS = 20V
68
NOTE: Heating effect of 2.0µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.25
ID = 250mA
1.15
3.0
VGS = 10V, ID = 2.5A
2.4
1.8
1.2
ON RESISTANCE
0.6
NORMALIZED DRAIN TO SOURCE
0.2
10
-40040
T
, JUNCTION TEMPERATURE (oC)
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
500
VGS= 0V, f = 1MHz
C
= CGS + C
400
C
C
ISS
RSS
OSS
= C
= CDS+ C
GD
GD
GD
80
120
160
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-40040
80
, JUNCTION TEMPERATURE (oC)
T
J
120160
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
2.0
VDS= 2 x VGS MAX, PULSE TEST = 80µs
1.6
= 25oC
T
J
1.2
0.8
0.4
, TRANSCONDUCTANCE (S)
fs
g
0
00.81.62.43.2
ID, DRAIN CURRENT (A)
TJ = 150oC
300
200
C, CAPACITANCE (pF)
100
0
C
ISS
C
OSS
C
RSS
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
1
TJ = 25oC
0.81.21.60.4
4.0
TJ = 150oC
0.1
, SOURCE TO DRAIN CURRENT (A)
DR
I
-2
10
0
VSD, SOURCE TO DRAIN VOLTAGE (V)
1001
2.0
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
5
Page 6
IRF614
Typical Performance Curves
20
16
12
8
, GATE TO SOURCE (V)
4
GS
V
0
036912
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
Unless Otherwise Specified (Continued)
ID = 5A
= 50V
V
DS
V
= 125V
DS
20
VDS = 200V
Q
, TOTAL GATE CHARGE (nC)
g(TOT)
V
DS
L
+
V
DD
-
DUT
16
BV
DSS
t
P
I
AS
V
DS
V
DD
0V
P
I
AS
0.01Ω
0
t
AV
t
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
ON
t
d(ON)
t
R
L
+
V
R
G
DUT
V
GS
DD
-
V
DS
90%
0
V
GS
10%
0
r
10%
50%
PULSE WIDTH
t
d(OFF)
90%
FIGURE 17. SWITCHING TIME TEST CIRCUITFIGURE 18. RESISTIVE SWITCHING WAVEFORMS
t
OFF
50%
t
f
90%
10%
6
Page 7
IRF614
Test Circuits and Waveforms
CURRENT
REGULATOR
12V
BATTERY
0
0.2µF
50kΩ
I
G(REF)
0.3µF
G
IG CURRENT
SAMPLING
RESISTORRESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT
(Continued)
V
DS
(ISOLATED
SUPPLY)
SAME TYPE
AS DUT
D
DUT
S
CURRENT
I
D
SAMPLING
V
DD
Q
g(TOT)
Q
gd
Q
gs
V
DS
0
V
DS
0
I
G(REF)
V
GS
FIGURE 20. GATE CHARGE WAVEFORMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
7
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