Datasheet IRF540ZPbF, IRF540ZSPbF, IRF540ZLPbF Datasheet

Features

Pulsed Drain C

c

Single Pulse Aval

gy

d

Single Pulse Aval

gy T

d Value

h

Aval

c

R

gy

g

l

Advanced Process Technology

l

Ultra Low On-Resistance

l

175°C Operating Temperature

l

Fast Switching

l

Repetitive Avalanche Allowed up to Tjmax

l

Lead-Free

PD - 95531A

IRF540ZPbF

IRF540ZSPbF

IRF540ZLPbF

HEXFET® Power MOSFET

D

V

= 100V

DSS

G

R

DS(on)

= 26.5mΩ

Description

This HEXFET® Power MOSFET utilizes the latest

S

ID = 36A

processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating.These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications.

TO-220AB

IRF540ZPbF

D2Pak

IRF540ZSPbF

TO-262

IRF540ZLPbF

Absolute Maximum Ratings

ID @ TC = 25°C

ID @ TC = 100°C

I

DM

PD @TC = 25°C

V

GS

E

AS (Thermally limited)

(Tested )

E

AS

I

AR

E

AR

T

J

T

STG

Parameter Units

Continuous Drain Current, V

urrent

Power Dissipation W

Linear Derating Factor W/°C Gate-to-Source Voltage V

anche Ener

anche Current

epetitive Avalanche Ener

Operating Junction and

Storage Temperature Range °C

Soldering Temperature, for 10 seconds

Mounting Torque, 6-32 or M3 screw



GS

@ 10V

este

i

(Silicon Limited)

See Fig.12a, 12b, 15, 16

300 (1.6mm from case )

Max.

140

0.61

± 20

120

-55 to + 175

y

10 lbf

in (1.1Nym)

36

25

92

83

A

mJ

A

mJ

Thermal Resistance

Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

R

JA

θ

Junction-to-Case

Case-to-Sink, Flat Greased Surface

Junction-to-Ambient

Junction-to-Ambient (PCB Mount)

i

j

––– 1.64 °C/W

0.50 –––

––– 62

––– 40

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07/23/10

IRF540Z/S/LPbF

/

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

V

(BR)DSS

∆

V

(BR)DSS

R

DS(on)

V

GS(th)

gfs Forward Transconductance 36 ––– ––– V I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

C

iss

C

oss

C

rss

C

oss

C

oss

C

eff.

oss

Source-Drain Ratings and Characteristics

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Drain-to-Source Breakdown Voltage 100 ––– ––– V

∆

T

Breakdown Voltage Temp. Coefficient ––– 0.093 ––– V/°C

J

Ω

Static Drain-to-Source On-Resistance ––– 21 26.5

m

Gate Threshold Voltage 2.0 ––– 4.0 V

Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250

Gate-to-Source Forward Leakage ––– ––– 200 nA

Gate-to-Source Reverse Leakage ––– ––– -200

Total Gate Charge ––– 42 63

Gate-to-Source Charge ––– 9.7 ––– nC

Gate-to-Drain ("Miller") Charge ––– 15 –––

Turn-On Delay Time ––– 15 –––

Rise Time ––– 51 –––

Turn-Off Delay Time ––– 43 ––– ns

Fall Time ––– 39 –––

Internal Drain Inductance ––– 4.5 ––– Between lead,

nH 6mm (0.25in.)

Internal Source Inductance ––– 7.5 ––– from package

Input Capacitance ––– 1770 –––

Output Capacitance ––– 180 –––

Reverse Transfer Capacitance ––– 100 ––– pF

Output Capacitance ––– 730 –––

Output Capacitance ––– 110 –––

Effective Output Capacitance ––– 170 –––

Parameter Min. Typ. Max. Units

Continuous Source Current ––– ––– 36

(Body Diode) A Pulsed Source Current ––– ––– 140

(Body Diode) Diode Forward Voltage ––– ––– 1.3 V

Reverse Recovery Time ––– 33 50 ns

Reverse Recovery Charge ––– 41 62 nC

Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

c

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, I

= 10V, ID = 22A

V

GS

= 1mA

D

e

VDS = VGS, ID = 250µA

= 25V, ID = 22A

V

DS

= 100V, VGS = 0V

V

DS

= 100V, VGS = 0V, TJ = 125°C

V

DS

= 20V

V

GS

= -20V

V

GS

I

= 22A

D

= 80V

V

DS

VGS = 10V

e

VDD = 50V

= 22A

I

D

Ω

= 12

R

G

VGS = 10V

and center of die contact

e

D

G

S

VGS = 0V

= 25V

V

DS

ƒ = 1.0MHz

VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

= 0V, VDS = 80V, ƒ = 1.0MHz

V

GS

= 0V, VDS = 0V to 80V

V

GS

f

Conditions

MOSFET symbol

showing the integral reverse

p-n junction diode. T

= 25°C, IS = 22A, VGS = 0V

J

TJ = 25°C, IF = 22A, VDD = 50V di/dt = 100A/µs

e

2 www.irf.com

IRF540Z/S/LPbF

1000

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

TOP 15V

100

BOTTOM 4.5V

10

1

0.1 1 10 100

VGS

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V 60µs PULSE WIDTH

Tj = 25°C

VDS, Drain-to-Source Voltage (V)

1000

)

Α

(

t n e

r

100

u C e

c

r u o S

o

t

-

10

n

i a

r D

,

D

I

TJ = 175°C

TJ = 25°C

V

= 25V

DS

60µs PULSE WIDTH

1

4.0 5.0 6.0 7.0

VGS, Gate-to-Source Voltage (V)

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

1000

TOP 15V

100

BOTTOM 4.5V

10

D

VGS

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

60µs PULSE WIDTH Tj = 175°C

1

0.1 1 10 100

0 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

80

) S

( e

c

60

n a

t c u d n o c s

40

n a

r T

d

r a

w

r o

20

F , s

f G

V

380µs PULSE WIDTH

0

0 1020304050

ID, Drain-to-Source Current (A)

DS

TJ = 175°C

TJ = 25°C

= 10V

Fig 3. Typical Transfer Characteristics

Fig 4. Typical Forward Transconductance

Vs. Drain Current

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IRF540Z/S/LPbF

3000

2500

) F

2000

p

( e

c n a

t

1500

i c a p a

C

1000

, C

500

0

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

+ Cgd, C

gs

gd

+ C

ds

iss

C

rss

C

oss

Ciss

Coss

Crss

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000.0

) A

( t

100.0

n e

r

r u

C n

i a

r

10.0

D e

s

r e v e

R ,

1.0

D S

I

0.1

TJ = 175°C

0.2 0.4 0.6 0.8 1.0 1.2 1.4

VSD, Source-toDrain Voltage (V)

ds

gd

TJ = 25°C

SHORTED

V

= 0V

GS

20

ID= 22A

) V

(

16

e g a

t

l o V

12

e c

r u o S

o

8

t

e

t a

G ,

S

4

G

V

VDS= 80V

VDS= 50V VDS= 20V

FOR TEST CIRCUIT SEE FIGURE 13

0

0 102030405060

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

) A

( t

100

n e

r

r u

C e

c

r u

10

o S

o

t

n

i a

r D

1

,

D

I

Tc = 25°C Tj = 175°C Single Pulse

0.1 1 10 100 1000

OPERATION IN THIS AREA LIMITED BY RDS(on)

V

, Drain-toSource Voltage (V)

DS

100µsec

1msec

10msec

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

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IRF540Z/S/LPbF

40

30

) A

( t n e

r

r u

C

20

n

i a

r D

,

D

I

10

0

25 50 75 100 125 150 175

TJ , Junction Temperature (°C)

Fig 9. Maximum Drain Current Vs.

Case Temperature

10

3.0

e c n a

t s

i s e

R n O e

)

c

d

r

e

u

z

i

o

l

S

a

m

o

t

r

-

o

n

i

N

(

a

r D

,

) n o

( S D

R

ID = 22A

V

= 10V

GS

2.5

2.0

1.5

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 10. Normalized On-Resistance

Vs. Temperature

)

C

1

J h

t

Z (

e s n o p s e

R l a

m

r e h T

0.001

D = 0.50

0.20

0.10

0.1

0.05

0.02

0.01

1E-006 1E-005 0.0001 0.001 0.01 0.1

SINGLE PULSE ( THERMAL RESPONSE )

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF540Z/S/LPbF

A

15V

DRIVER

+

V

DD

-

R

20V

V

DS

G

GS

L

D.U.T

I

AS

Ω

0.01

t

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

I

AS

Fig 12b. Unclamped Inductive Waveforms

Q

G

10 V

Q

GS

Q

GD

180

) J

m

160

( y

g

r

140

e n E

e

120

h c n a

l

100

a v

A

80

e s

l u P

60

e

l g n

i

40

S ,

S

20

A

E

0

25 50 75 100 125 150 175

TOP 8.3A

BOTTOM20A

Starting TJ , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

4.0

I

D

14A

) V

V

G

Charge

Fig 13a. Basic Gate Charge Waveform

L

0

1K

DUT

VCC

(

3.5

e g a

t

l o V

d

l

3.0

o h s e

r h

t

2.5

e

t a

G

) h

t

(

2.0

S G

V

1.5

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 250µA

TJ , Temperature ( °C )

Fig 13b. Gate Charge Test Circuit

Fig 14. Threshold Voltage Vs. Temperature

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IRF540Z/S/LPbF

1000

Duty Cycle = Single Pulse

100

) A

( t n e

r

r u

C

10

e h c n a

l a v A

1

0.1

1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

0.01

0.05

0.10

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆ Tj = 25°C due to avalanche losses

100

90

)

80

J m

( y

70

g

r e n

60

E e

h

50

c n a

l

40

a v

A ,

30

R A

20

E

10

0

25 50 75 100 125 150 175

TOP Single Pulse BOTTOM 10% Duty Cycle ID = 20A

Starting TJ , Junction Temperature (°C)

Fig 16. Maximum Avalanche Energy

Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T every part type.

2. Safe operation in Avalanche is allowed as long asT not exceeded.

. This is validated for

jmax

3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.

4. P

avalanche pulse.

= Average power dissipation per single

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ∆T = Allowable rise in junction temperature, not to exceed

T

(assumed as 25°C in Figure 15, 16).

jmax

t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see figure 11)

thJC

P

= 1/2 ( 1.3·BV·Iav) = DT/ Z

D (ave)

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

·f

av

D (ave)·tav

thJC

www.irf.com 7

is

IRF540Z/S/LPbF





Reverse Recovery Current

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied Voltage

+

-

Period

P.W.

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

R

D.U.T.

D

+

V

DD

-

V

DS

V

GS

R

G

10V

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

V

DS

90%

10% V

GS

t

d(on)tr

t

d(off)tf

Fig 18b. Switching Time Waveforms

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TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

IRF540Z/S/LPbF

TO-220AB Part Marking Information

EXAMP LE: THIS IS AN IRF 1010

Note: "P" in assembly line position

LOT CODE 1789 ASS EMBL ED ON WW 19, 2000 IN THE ASSEMBLY LINE "C"

indi cates "L ead - F ree"

INTE RNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

TO-220AB package is not recommended for Surface Mount Application

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

www.irf.com 9

PART NUMBER

DAT E CODE YEAR 0 = 2000 WEEK 19 LINE C

IRF540Z/S/LPbF

2

Pak (TO-263AB) Package Outline

D

Dimensions are shown in millimeters (inches)

D2Pak (TO-263AB) Part Marking Information

THI S IS AN IRF530S WITH LOT CODE 8024

AS SE MB L ED ON WW 02, 200 0 IN TH E ASSE MBLY LI NE "L"

INTE RNATIONAL

RE CTIF IER

LOGO

AS S E M B L Y LOT CODE

F530S

OR

INTE RNATIONAL

RE CTIF IER

LOGO

AS S E M B L Y LOT CODE

F530S

PART NUMBER

DATE CODE P = DESIGNATES LEAD - FREE

YEAR 0 = 2000 WEE K 02 A = AS S EMB L Y S IT E COD E

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

10 www.irf.com

PART NUMBER

DATE CODE YEAR 0 = 2000 WEEK 02 LINE L

PRODUCT (OPTIONAL)

TO-262 Package Outline

Dimensions are shown in millimeters (inches)

IRF540Z/S/LPbF

TH IS IS AN I RL3103L

EXAMPLE:

LOT CODE 1789

ASS E MB LE D ON WW 19, 1997

IN THE ASS EMBLY LINE "C"

Note: "P" in assembly line posi tion indicates "L ead-Fr ee"

INTE RNATIONAL

RECTIF IER

LOGO

ASSEMBLY LOT CODE

PART NUMBER

DATE CODE YEAR 7 = 1997 WE EK 19 LINE C

OR

INTE RNATIONAL

RECTIF IER

LOGO

ASSEMBLY LOT CODE

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

www.irf.com 11

PART NUMBER

DATE CODE P = DESIGNATE S LEAD-FREE

PRODUCT (OPTIONAL)

YEAR 7 = 1997 WE EK 19

A = AS SE MB LY S IT E CODE

IRF540Z/S/LPbF

D2Pak Tape & Reel Infomation

TRR

FEED DIRECTION

TRL

1.85 (.073)

1.65 (.065)

10.90 (.42 9)

10.70 (.42 1)

4.10 (.161)

3.90 (.153)

1.60 (.063)

1.50 (.059)

11.60 (.457 )

11.40 (.449 )

16.10 (.634)

15.90 (.626)

1.60 (.0 63)

1.50 (.0 59)

1.75 (.069)

1.25 (.049)

15.42 (.6 09)

15.22 (.6 01)

0.368 (. 0145)

0.342 (. 0135)

24.30 (. 957)

23.90 (. 941)

4.72 (.136)

4.52 (.178)

13.50 (.532)

12.80 (.504)

330.00 (14.173) MAX.

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

27.40 (1.079)

23.90 (.941)

4

26.40 (1.039)

24.40 (.961)

3

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by T

RG = 25Ω, I

, starting TJ = 25°C, L = 0.46mH

Jmax

= 20A, VGS =10V. Part not

AS

recommended for use above this value.

 Pulse width ≤ 1.0ms; duty cycle ≤ 2%.  C

eff. is a fixed capacitance that gives the

oss

same charging time as C from 0 to 80% V

DSS

.

oss

while V

is rising

DS

 Limited by T

avalanche performance.

 This value determined from sample failure population. 100%

tested to this value in production.

 This is only applied to TO-220AB pakcage.  This is applied to D

4 or G-10 Material). For recommended footprint and soldering

techniques refer to application note #AN-994.

, see Fig.12a, 12b, 15, 16 for typical repetitive

Jmax

TO-220AB package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

60.00 (2.362) MIN.

30.40 (1.197) MAX.

4

2

Pak, when mounted on 1" square PCB (FR-

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 07/2010

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