Datasheet IRF540NSPbF, IRF540NLPbF Datasheet

Page 1
PD - 95130
IRF540NSPbF
l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 175°C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free
Description
Advanced HEXFET® Power MOSFETs from International Rectifier utilize advanced processing
G
IRF540NLPbF
HEXFET® Power MOSFET
D
S
V
R
DS(on)
= 100V
= 44mΩ
ID = 33A
techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.
The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on­resistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF540NL) is available for low­profile applications.
D2Pak
IRF540NSPbF
TO-262
IRF540NLPbF
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 33 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 23 A I
DM
PD @TC = 25°C Power Dissipation 130 W
V
GS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt  7.0 V/ns T
J
T
STG
Pulsed Drain Current  110
Linear Derating Factor 0.87 W/°C Gate-to-Source Voltage ± 20 V Avalanche Current 16 A Repetitive Avalanche Energy 13 mJ
Operating Junction and -55 to + 175 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)
°C
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
www.irf.com 1
Junction-to-Case ––– 1.15 Junction-to-Ambient (PCB mount)** ––– 40
°C/W
3/18/04
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IRF540NS/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
E
AS
Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.12 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance ––– ––– 44 mΩ VGS = 10V, ID = 16A Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA Forward Transconductance 21 ––– ––– S VDS = 50V, ID = 16A
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C Gate-to-Source Forward Leakage ––– ––– 100 V Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 100V, VGS = 0V
µA
= 20V
GS
nA
VGS = -20V Total Gate Charge ––– ––– 71 ID = 16A Gate-to-Source Charge ––– ––– 14 nC VDS = 80V Gate-to-Drain ("Miller") Charge ––– ––– 21 VGS = 10V, See Fig. 6 and 13  Turn-On Delay Time ––– 11 ––– VDD = 50V Rise Time ––– 35 ––– ID = 16A Turn-Off Delay Time ––– 39 ––– RG = 5.1Ω
ns
Fall Time ––– 35 ––– VGS = 10V, See Fig. 10
4.5
Internal Drain Inductance
Internal Source Inductance ––– –––
––– –––
7.5
Between lead,
6mm (0.25in.)
nH
from package
and center of die contact Input Capacitance ––– 1960 ––– VGS = 0V Output Capacitance ––– 250 ––– VDS = 25V Reverse Transfer Capacitance ––– 40 ––– pF ƒ = 1.0MHz, See Fig. 5 Single Pulse Avalanche Energy ––– 700185mJ I
= 16A, L = 1.5mH
AS
D
G
S
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode)
––– –––
––– –––
33
110
showing the
A
p-n junction diode.
G
Diode Forward Voltage ––– ––– 1.2 V TJ = 25°C, IS = 16A, VGS = 0V Reverse Recovery Time ––– 115 170 ns TJ = 25°C, IF = 16A Reverse Recovery Charge ––– 505 760 nC di/dt = 100A/µs

Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Starting T
RG = 25Ω, I
I
SD
= 25°C, L =1.5mH
J
= 16A. (See Figure 12)
AS
≤ 16A, di/dt ≤ 340A/µs, V
DD
≤ V
(BR)DSS
TJ ≤ 175°C
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This is a typical value at device destruction and represents
operation outside rated limits.
This is a calculated value limited to TUses IRF540N data and test conditions.
,
**When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994
= 175°C .
J
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D
S
Page 3
IRF540NS/LPbF
1000
100
10
D
I , Drain-to-Source Current (A)
1
0.1 1 10 100
1000
VGS
TOP
15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20µs PULSE WIDTH T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
°
1000
100
TOP
BOTTOM
VGS 15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
10
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
°
T = 175 C
1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.5
I =
D
33A
3.0
2.5
°
T = 25 C
100
D
I , Drain-to-Source Current (A)
10
4.0 5.0 6.0 7.0 8.0 9.0
J
°
T = 175 C
J
V = 50V
DS
20µs PULSE WIDTH
V , Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
GS
°
10V
Vs. Temperature
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Page 4
IRF540NS/LPbF
3000
2500
2000
1500
1000
C, Capacitance (pF)
500
0
1 10 100
V
=
0V,
GS
C
=
iss gs gd , ds
C
=
rss gd
C
=
oss ds gd
V , Drain-to- Source Voltage ( V)
DS
f = 1MHz
C
+ C C C
C
iss
C
oss
C
rss
C SHORTED
+ C
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
100
°
T = 175 C
J
10
°
T = 25 C
J
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.6 1.0 1.4 1.8
V ,Source-to-Drain Voltage (V)
SD
V = 0 V
GS
20
I =
16A
D
V = 80V
DS
V = 50V
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
0
0 20 40 60 80
Q , Total Gate Charge (nC)
G
DS
V = 20V
DS
FOR TEST CIRCUIT
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA
) A
( t
100
n e
r r
u C e
c r
u
10
o S
­o
t
­n
i a
r D
1
, I
D
TA = 25°C
TJ = 175°C
Single Pulse
0.1 1 10 100 1000
V
LIMITED BY RDS(on)
, Drain-toSource Voltage (V)
DS
100µsec
13
1msec
10msec
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
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Page 5
IRF540NS/LPbF
35
30
25
20
15
D
10
I , Drain Current (A)
5
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
R
V
DS
V
GS
R
G
V
GS
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
D
D.U.T.
Fig 10a. Switching Time Test Circuit
V
DS
90%
10% V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
+
V
DD
-
thJC
1
D = 0.50
0.20
1 2
P
DM
t
1
t
2
0.10
0.1
0.05
0.02
Thermal Response (Z )
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 6
IRF540NS/LPbF
A
15V
DRIVER
R
G
20V
V
DS
t
L
D.U.T
I
AS
Ω
0.01
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
400
TOP
300
+
V
DD
-
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting T , Junction Temperature ( C)
J
BOTTOM
I
D
6.5A
11.3A 16A
°
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Current Regulator
Same Type as D.U.T.
50KΩ
Q
G
V
GS
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
12V
Fig 13b. Gate Charge Test Circuit
.2µF
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
I
D
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+
V
DS
-
Page 7
IRF540NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance Current Transformer
-
+
-
-
+
R
G
V
GS
• dv/dt controlled by R
• ISD controlled by Duty Factor "D"
G
• D.U.T. - Device Under Test
+
V
DD
-
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D =
P. W .
Period
VGS=10V
[ ] ***
D.U.T. ISDWaveform
Reverse Recovery Current
Re-Applied Voltage
D.U.T. VDSWaveform
Inductor Curent
*** V
= 5.0V for Logic Level and 3V Drive Devices
GS
Fig 14. For N-channel HEXFET
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
®
power MOSFETs
V
DD
[ ]
I
[ ]
SD
www.irf.com 7
Page 8
IRF540NS/LPbF
2
D
Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 530S WIT H LOT CODE 8024
AS S E MB LE D ON W W 02, 2000 IN THE ASS EMBLY LINE "L"
N ote: "P" in as sem bly line
po s iti on in di cates "L ead-F ree"
INT ER NAT ION AL
R E CT IF IER
LOGO
ASSEMBLY LOT CODE
F530S
PART NUMBE R
DATE CODE YE AR 0 = 2000 WEE K 02 LINE L
OR
IN T ER NA T IONA L
RECTIFIER
LOGO
AS S EM B LY LOT CODE
F 530S
8 www.irf.com
PART NUMB ER
DATE CODE P = DESIGNATE S LE AD-F REE
PRODUCT (OPTIONAL)
YEAR 0 = 2000 WEEK 02
A = ASSEMBLY SITE CODE
Page 9
TO-262 Package Outline
IRF540NS/LPbF
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
TH IS IS AN I RL3103L
EXAMPLE:
LOT CODE 1789 ASS EMBLE D ON WW 19, 1997 IN T HE ASSEMBLY LINE "C"
Note: "P" in ass embl y line pos iti on indi cates "L ead-F ree"
INTE RNAT IONAL
RECT IFIER
LOGO
AS S E MB L Y LOT CODE
PART NUMBE R
DATE CODE YEAR 7 = 1997 WEEK 19 LINE C
OR
INTE RNATIONAL
RECT IFIE R
LOGO
ASSEMBLY LOT CODE
www.irf.com 9
PART NUMB ER
DAT E CODE P = DES IGNATE S L EAD-F REE
PRODUCT (OPT IONAL)
YEAR 7 = 1997 WE EK 19
A = ASSEMBLY SITE CODE
Page 10
IRF540NS/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
FEED DI RECTION
TRL
FEED DI RECTION
1.85 (.073)
1.65 (.065)
10.90 (.429)
10.70 (.421)
4.10 (.161)
3.90 (.153)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
16.10 (.634)
15.90 (.626)
1.60 (.063)
1.50 (.059)
1.75 (.069)
1.25 (.049)
15.42 (.609)
15.22 (.601)
0.368 (.0145)
0.342 (.0135)
24.30 (.957)
23.90 (.941)
4.72 (.136)
4.52 (.178)
13.50 ( .532)
12.80 ( .504)
330.00 (14.173) MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
27.40 ( 1.079)
23.90 ( .941)
4
26.40 ( 1.03 9)
24.40 ( .961 )
3
60.00 (2.362) MIN.
30.40 ( 1.197) MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/04
10 www.irf.com
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