Datasheet IRF4905SPBF Datasheet

PD - 97034

IRF4905SPbF

IRF4905LPbF

Features

O Advanced Process Technology O Ultra Low On-Resistance O 150°C Operating Temperature O Fast Switching O Repetitive Avalanche Allowed up to Tjmax O Some Parameters Are Differrent from

IRF4905S

O Lead-Free

Description

G

HEXFET® Power MOSFET

D

S

D

V

DSS

R

DS(on)

ID = -42A

D

= -55V

= 20mΩ

Features of this design are a 150°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in a wide variety of other applications.

D2Pak

IRF4905SPbF

GDS

S

D

G

S

D

G

TO-262

IRF4905LPbF

Gate Drain Source

Absolute Maximum Ratings

ID @ TC = 25°C

ID @ TC = 100°C

@ TC = 25°C

I

D

I

DM

PD @TC = 25°C

V

GS

E

AS (Thermally limited)

(Tested )

E

AS

I

AR

E

AR

T

J

T

STG

Parameter Units

Continuous Drain Current, V

Pulsed Drain Current

Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Single Pulse Avalanche Energy

Single Pulse Avalanche Energy Tested Value

Avalanche Current

Repetitive Avalanche Energy

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds

Mounting Torque, 6-32 or M3 screw

c

c

@ 10V (Silicon Limited)

GS

@ 10V (Silicon Limited)

GS

@ 10V (Package Limited)

GS

d

g

i

h

See Fig.12a, 12b, 15, 16

300 (1.6mm from case )

Max.

-70

-44

-42

-280

170

1.3

± 20

140

790

-55 to + 150

10 lbf

y

in (1.1Nym)

A

W

W/°C

V

mJ

A

mJ

°C

Thermal Resistance

Parameter Typ. Max.

R

θJC

R

θJA

Junction-to-Case

Junction-to-Ambient (PCB Mount, steady state)

j

ij

––– 0.75

––– 40

Units

www.irf.com 1

8/5/05

IRF4905S/L

r

z

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

V

(BR)DSS

∆V

(BR)DSS

R

DS(on)

V

GS(th)

gfs Forward Transconductance 19 ––– ––– S

I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

S

C

iss

C

oss

C

rss

C

oss

C

oss

C

eff.

oss

Drain-to-Source Breakdown Voltage -55 ––– ––– V

/∆T

Breakdown Voltage Temp. Coefficient ––– -0.054 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– ––– 20

mΩ

Gate Threshold Voltage -2.0 ––– -4.0 V

Drain-to-Source Leakage Current ––– ––– -25 µA

––– ––– -200

Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

Total Gate Charge ––– 120 180

Gate-to-Source Charge ––– 32 ––– nC

Gate-to-Drain ("Miller") Charge ––– 53 –––

Turn-On Delay Time ––– 20 –––

Rise Time ––– 99 –––

Turn-Off Delay Time ––– 51 ––– ns

Fall Time ––– 64 –––

Internal Source Inductance ––– 7.5 ––– nH Between lead,

Input Capacitance ––– 3500 –––

Output Capacitance ––– 1250 –––

Reverse Transfer Capacitance ––– 450 ––– pF

Output Capacitance ––– 4620 –––

Output Capacitance ––– 940 –––

Effective Output Capacitance ––– 1530 –––

Conditions

VGS = 0V, ID = -250µA

Reference to 25°C, I

V

= -10V, ID = -42A

GS

VDS = VGS, ID = -250µA

VDS = -25V, ID = -42A

V

= -55V, VGS = 0V

DS

V

= -44V, VGS = 0V, TJ = 125°C

DS

= -20V

V

GS

V

= 20V

GS

= -42A

I

D

V

= -44V

DS

VGS = -10V

e

VDD = -28V

I

= -42A

D

R

= 2.6 Ω

G

VGS = -10V

e

and center of die contact

VGS = 0V

V

= -25V

DS

ƒ = 1.0MHz

= 0V, VDS = -1.0V, ƒ = 1.0MH

V

GS

VGS = 0V, VDS = -44V, ƒ = 1.0MHz

V

= 0V, VDS = 0V to -44V

GS

= -1mA

D

e

f

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units

I

S

Continuous Source Current ––– ––– -42

(Body Diode) A

I

SM

V

SD

t

r

Q

r

t

on

Pulsed Source Current ––– ––– -280

(Body Diode)

c

Diode Forward Voltage ––– ––– -1.3 V

Reverse Recovery Time ––– 61 92 ns

Reverse Recovery Charge ––– 150 220 nC

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

MOSFET symbol

showing the

integral reverse

p-n junction diode.

T

= 25°C, IS = -42A, VGS = 0V

J

TJ = 25°C, IF = -42A, VDD = -28V

di/dt = -100A/µs

Conditions

e

2 www.irf.com

IRF4905S/L

1000

) A

( t n e

r

r u

100

C e

c

r u o S

o

t

n

i

10

a

r D

,

D

I

-

-4.5V

TOP -15V

BOTTOM -4.5V

≤

60µs PULSE WIDTH

Tj = 25°C

1

0.1 1 10 100 1000

-VDS, Drain-to-Source Voltage (V)

1000.0

)

Α

(

t n

100.0

e

r

r u

C e

c

r u

10.0

o S

o

t

n

i a

r D

1.0

,

D

I

-

0.1

3 4 5 6 7 8 9 10 11 12 13 14

TJ = 25°C

TJ = 150°C

V

= -25V

DS

≤

60µs PULSE WIDTH

-VGS, Gate-to-Source Voltage (V)

VGS

-10V

-8.0V

-7.0V

-6.0V

-5.5V

-5.0V

1000

) A

( t n e

r

r u

100

C e

c

r u o S

o

t

n

i

10

a

r D

,

D

I

-

-4.5V

TOP -15V

BOTTOM -4.5V

≤

60µs PULSE WIDTH

Tj = 150°C

1

0.1 1 10 100 1000

-VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

40

) S

( e

c n

30

a

t c u d n o c s n

20

a

r T

d

r a

w

r o

10

F , s

f G

V

DS

380µs PULSE WIDTH

0

0 20406080

-ID, Drain-to-Source Current (A)

TJ = 25°C

TJ = 150°C

= -10V

VGS

-10V

-8.0V

-7.0V

-6.0V

-5.5V

-5.0V

Fig 3. Typical Transfer Characteristics

Fig 4. Typical Forward Transconductance

Vs. Drain Current

www.irf.com 3

IRF4905S/L

7000

6000

)

5000

F p

( e

c

4000

n a

t

i c a

3000

p a

C ,

C

2000

1000

0

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

iss

rss

oss

= C

gs

gd

ds

C

Ciss

Coss

Crss

+ Cgd, C

+ C

-VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000.0

) A

( t

100.0

n e

r

r u

C n

i a

r

10.0

D e

s

r e v e

R ,

D S

I

-

TJ = 150°C

1.0

0.1

0.0 0.4 0.8 1.2 1.6 2.0

TJ = 25°C

-VSD, Source-to-Drain Voltage (V)

gd

SHORTED

ds

V

GS

= 0V

20

ID= -42A

) V

( e

16

g a

t

l o V

e

12

c

r u o S

o

t

-

8

e

t a

G ,

S

4

G

V

-

VDS= -44V

VDS= -28V VDS= -11V

0

0 40 80 120 160 200

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

) A

( t n e

r

r u

100

C e

c

r u o S

o

t

n

i

10

a

r D

,

D

I

-

Tc = 25°C Tj = 150°C Single Pulse

1

0 1 10 100

OPERATION IN THIS AREA LIMITED BY RDS(on)

LIMITED BY PACKAGE

-V

, Drain-toSource Voltage (V)

DS

1msec

100µsec

10msec

DC

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

4 www.irf.com

IRF4905S/L

τ

80

LIMITED BY PACKAGE

)

60

A

( t n e

r

r u

C

40

n

i a

r D

,

D

I

-

20

0

25 50 75 100 125 150

TC , Case Temperature (°C)

Fig 9. Maximum Drain Current Vs.

Case Temperature

1

2.0

e c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D

,

) n o

( S D

R

ID = -42A

V

= -10V

GS

1.5

) d e z

i

l a

m

r o

N

(

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

Fig 10. Normalized On-Resistance

Vs. Temperature

)

C J h

t

0.1

Z (

e s n o p s e

R l a

0.01

m

r e h T

0.001

1E-006 1E-005 0.0001 0.001 0.01 0.1

0.20

0.10

0.05

0.02

0.01

SINGLE PULSE ( THERMAL RESPONSE )

τ

J

τ

J

τ

1

τ

1

Ci= τi/Ri

R

1

R

1

R

2

3

R

2

τ

2

τ

2

Ri (°C/W) τi (sec)

R

3

τ

C

τ

3

0.1165 0.000068

0.3734 0.002347

τ

3

0.2608 0.014811

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com 5

D = 0.50

IRF4905S/L

(BR)

A

L

D.U.T

I

AS

0.01

p

DRIVER

Ω

15V

V

DD

R

V

G

-20V

DS

t

Fig 12a. Unclamped Inductive Test Circuit

I

AS

t

p

V

DSS

Fig 12b. Unclamped Inductive Waveforms

Q

G

10V

Q

GS

V

G

Q

GD

Charge

Fig 13a. Basic Gate Charge Waveform

Current Regulator

Same Type as D.U.T.

50KΩ

.2µF

12V

V

GS

-3mA

.3µF

D.U.T.

V

DS

+

600

) J

m

( y

500

g

r e n E

e

400

h c n a

l a v

300

A e

s

l u P

200

e

l g n

i S

100

, S A

E

0

25 50 75 100 125 150

I

TOP

-30A

BOTTOM

Starting TJ, Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

3.6

) V

( e

g a

3.2

t

l o V

d

l o h s e

2.8

r h

t e

t a

G

) h

t

2.4

( S G

V

-

2.0

-75 -50 -25 0 25 50 75 100 125 150

TJ , Temperature ( °C )

ID = -250µA

D

-17A

-42A

I

Current Sampling R esistors

Fig 13b. Gate Charge Test Circuit

I

G

D

Fig 14. Threshold Voltage Vs. Temperature

6 www.irf.com

IRF4905S/L

1000

Duty Cycle = Single Pulse

100

) A

( t n e

r

r u

C

10

e h c n a

l a v A

1

0.1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

0.01

0.05

0.10

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆Tj = 25°C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax

160

TOP Single Pulse

) J

m

120

( y

g

r e n E

e h

80

c n a

l a v A ,

R

40

A

E

BOTTOM 1% Duty Cycle ID = -42A

Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T

. This is validated for

jmax

every part type.

2. Safe operation in Avalanche is allowed as long asT

jmax

not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.

4. P

= Average power dissipation per single

D (ave)

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ∆T = Allowable rise in junction temperature, not to exceed

T

(assumed as 25°C in Figure 15, 16).

0

25 50 75 100 125 150

Starting TJ , Junction Temperature (°C)

Fig 16. Maximum Avalanche Energy

Vs. Temperature

jmax

t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see figure 11)

thJC

P

= 1/2 ( 1.3·BV·Iav) = DT/ Z

D (ave)

I

2DT/ [1.3·BV·Zth]

av =

E

AS (AR)

= P

·f

av

D (ave)·tav

thJC

www.irf.com 7

is

IRF4905S/L

D.U.T**

+



-

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-



R

G

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

** Reverse Polarity of D.U.T for P-Channel

Fig 17. Peak Diode Recovery dv/dt Test Circuit for P-Channel

R

G

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

Reverse Recovery

+

-

Current

Re-Applied Voltage

D.U.T. VDSWaveform

Inductor Curent

* V

= 5V for Logic Level Devices

GS

+

V

DD

HEXFET® Power MOSFETs

R

D.U.T.

D

-

+

V

DS

V

GS

Period

Body Diode Forward

Current

Diode Recovery

Body Diode Forward Drop

Ripple ≤ 5%

V

DD

dv/dt

di/dt

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

V

GS

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

V

GS

10%

90%

V

DS

t

d(on)tr

t

d(off)tf

Fig 18b. Switching Time Waveforms

8 www.irf.com

2

D

Pak Package Outline (Dimensions are shown in millimeters (inches))

IRF4905S/L

D2Pak Part Marking Information

T HIS IS AN IRF 530S WIT H

LOT CODE 8024 ASS EMBLE D ON WW 02, 2000 IN THE ASSEMBLY LINE "L"

Note: "P" in as sembly line posi tion indicates "Lead-F ree"

INTE RNATIONAL

RECTIF IER

LOGO

ASSEMBLY LOT CODE

F530S

OR

INTE RNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

www.irf.com 9

F530S

PART NUMBER

DATE CODE YEAR 0 = 2000 WEEK 02 LINE L

PART NUMBER

DATE CODE P = D ES I GN AT ES L E AD- F RE E

PRODUCT (OPTIONAL )

YEAR 0 = 2000 WEEK 02

A = ASSEMBLY SITE CODE

IRF4905S/L

TO-262 Package Outline (Dimensions are shown in millimeters (inches))

IGBT

1- GATE

2- COLLECTOR

3- EMITTER

4- COLLECTOR

TO-262 Part Marking Information

TH IS I S AN IRL 3103L

EXAMPLE:

LOT CODE 1789 ASS EMBL ED ON WW 19, 1997 IN THE ASSEMBLY LINE "C"

Note: "P" in as sembly line pos i tio n in dicates "L ead-F r ee"

INTERNATIONAL

RECTIFIER

LOGO

AS S E MB L Y LOT CODE

PART NUMBER

DATE CODE YEAR 7 = 1997 WE EK 19 LINE C

OR

INTERNATIONAL

RECTIFIER

LOGO

AS S E MB L Y LOT CODE

10 www.irf.com

PART NUMBER

DATE CODE P = DE S IGN ATE S L EAD -F RE E

PRODUCT (OPT IONAL )

YEAR 7 = 1997 WEEK 19

A = AS S E MB LY SI T E COD E

D2Pak Tape & Reel Information

TRR

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

FEED DIRECTION

TRL

FEED DIRECTION

1.85 (.073)

1.65 (.065)

10.90 (.429)

10.70 (.421)

11.60 (.457)

11.40 (.449)

16.10 (.634)

15.90 (.626)

1.60 (.063)

1.50 (.059)

1.75 (.069)

1.25 (.049)

15.42 (.609)

15.22 (.601)

0.368 (.0145)

0.342 (.0135)

24.30 (.957)

23.90 (.941)

4.72 (.136)

4.52 (.178)

IRF4905S/L

13.50 (.532)

12.80 (.504)

330.00 (14.173) MAX.

NOTES :

1. COMFOR MS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by T

RG = 25Ω, I

, starting TJ = 25°C, L = 0.16mH

Jmax

= -42A, VGS =-10V. Part not

AS

recommended for use above this value.

 Pulse width ≤ 1.0ms; duty cycle ≤ 2%.  C

eff. is a fixed capacitance that gives the

oss

same charging time as C from 0 to 80% V

DSS

.

oss

while V

DS

is rising

This product has been designed and qualified for the Industrial market.

27.40 (1.079)

23.90 (.941)

4

60.00 (2.362) MIN.

30.40 (1.197) MAX.

4

, see Fig.12a, 12b, 15, 16 for typical repetitive

 Limited by T

26.40 (1.039)

24.40 (.961)

3

Jmax

avalanche performance.

 This value determined from sample failure population. 100%

tested to this value in production.

 This is applied to D

4 or G-10 Material). For recommended footprint and soldering

techniques refer to application note #AN-994.

 R

is measured at TJ approximately 90°C

θ

2

Pak, when mounted on 1" square PCB (FR-

Data and specifications subject to change without notice.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 08/05

www.irf.com 11

Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/