Datasheet IRF4104SPBF Datasheet

Pulsed Drain C

c

Single Pulse Aval

gy

d

Single Pulse Aval

gy T

d Value

h

Aval

c

R

gy

g

PD - 95468A

IRF4104PbF

IRF4104SPbF

IRF4104LPbF

Features

l

Advanced Process Technology

l

Ultra Low On-Resistance

l

175°C Operating Temperature

l

Fast Switching

l

Repetitive Avalanche Allowed up to Tjmax

l

Lead-Free

G

Description

This HEXFET® Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications.

Absolute Maximum Ratings

ID @ TC = 25°C

ID @ TC = 100°C

I

@ TC = 25°C

D

I

DM

PD @TC = 25°C

V

GS

E

AS (Thermally limited)

(Tested )

E

AS

I

AR

E

AR

T

J

T

STG

Continuous Drain Current, V

urrent

Power Dissipation W

Linear Derating Factor W/°C Gate-to-Source Voltage V

anche Ener

anche Current

epetitive Avalanche Ener

Operating Junction and

Storage Temperature Range °C

Soldering Temperature, for 10 seconds

Mounting Torque, 6-32 or M3 screw



Parameter Units

(Silicon Limited)

@ 10V

GS

@ 10V

GS

(Package limited)

@ 10V

GS

este

i

TO-220AB

IRF4104PbF

Thermal Resistance

Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

R

JA

θ

Junct ion-to-Case

Case-to-Sink, Flat Greased Surface

Junct ion-to-Ambient

Junct ion-to-Ambient (PCB Mount)

i

j

www.irf.com 1

HEXFET® Power MOSFET

D

V

= 40V

DSS

R

S

D2Pak

IRF4104SPbF

Max.

120

84

75

470

140

0.95

± 20

120

220

See Fig.12a, 12b, 15, 16

-55 to + 175

300 (1.6mm from case )

y

in (1.1Nym)

10 lbf

––– 1.05 °C/W

0.50 –––

––– 62

––– 40

DS(on)

I

D

= 75A

= 5.5mΩ

TO-262

IRF4104LPbF

A

mJ

A

mJ

07/23/10

IRF4104S/LPbF

/

µ

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

V

(BR)DSS

∆V

(BR)DSS

R

DS(on)

V

GS(th)

gfs Forward Transconductance 63 ––– ––– V I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

C

iss

C

oss

C

rss

C

oss

C

oss

eff.

C

oss

Source-Drain Ratings and Characteristics

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Drain-to-Source Breakdown Voltage 40 ––– ––– V

∆T

Breakdown Voltage Temp. Coefficient ––– 0.032 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 4.3 5.5

mΩ

Gate Threshold Voltage 2.0 ––– 4.0 V

Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250

Gate-to-Source Forward Leakage ––– ––– 200 nA

Gate-to-Source Reverse Leakage ––– ––– -200

Total Gate Charge ––– 68 100

Gate-to-Source Charge ––– 21 ––– nC

Gate-to-Drain ("Miller") Charge ––– 27 –––

Turn-On Delay Time ––– 16 –––

Rise Time ––– 130 –––

Turn-Off Delay Time ––– 38 ––– ns

Fall Time ––– 77 –––

Internal Drain Inductance ––– 4.5 ––– Between lead,

nH 6mm (0.25in.)

Internal Source Inductance ––– 7.5 ––– from package

Input Capacitance ––– 3000 –––

Output Capacitance ––– 660 –––

Reverse Transfer Capacitance ––– 380 ––– pF

Output Capacitance ––– 2160 –––

Output Capacitance ––– 560 –––

Effective Output Capacitance ––– 850 –––

Parameter Min. Typ. Max. Units

Continuous Source Current ––– ––– 75

(Body Diode) A Pulsed Source Current ––– ––– 470

(Body Diode) Diode Forward Voltage ––– ––– 1.3 V

Reverse Recovery Time ––– 23 35 ns

Reverse Recovery Charge ––– 6.8 10 nC

Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

c

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, I

= 10V, ID = 75A

V

GS

= 1mA

D

e

VDS = VGS, ID = 250µA

VDS = 10V, ID = 75A

V

= 40V, VGS = 0V

DS

= 40V, VGS = 0V, TJ = 125°C

V

DS

= 20V

V

GS

= -20V

V

GS

I

= 75A

D

= 32V

V

DS

VGS = 10V

e

VDD = 20V

= 75A

I

D

= 6.8 Ω

R

G

VGS = 10V

e

and center of die contact VGS = 0V

= 25V

V

DS

ƒ = 1.0MHz

V

= 0V, VDS = 1.0V, ƒ = 1.0MHz

GS

= 0V, VDS = 32V, ƒ = 1.0MHz

V

GS

= 0V, VDS = 0V to 32V

V

GS

f

Conditions

MOSFET symbol

showing the integral reverse

p-n junction diode. T

= 25°C, IS = 75A, VGS = 0V

J

TJ = 25°C, IF = 75A, VDD = 20V

s

di/dt = 100A/

e

2 www.irf.com

IRF4104S/LPbF

1000

) A

( t

100

n e

r

r u

C e

c

r

10

u o S

o

t

n

i a

r

1

D ,

D

I

4.5V

20µs PULSE WIDTH

0.1

0.1 1 10 100

Tj = 25°C

VDS, Drain-to-Source Voltage (V)

1000

V

TOP 15V 10V

7.0V

6.0V

5.5V

5.0V BOTTOM 4.5V

GS

8.0V

1000

V

TOP 15V

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

10V

7.0V

6.0V

5.5V

5.0V BOTTOM 4.5V

100

D

10

0.1 1 10 100

GS

8.0V

4.5V

20µs PULSE WIDTH Tj = 175°C

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

120

) A

(

t n e

r

100

r u

C e

c

r u o S

o

t

-

10

n

i a

r D

,

D

I

1

4 6 8 10 12

TJ = 25°C

TJ = 175°C

V

= 15V

DS

20µs PULSE WIDTH

VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

) S

(

100

e c n a

t c

80

u d n o c s

60

n a

r T

d

r a

40

w

r o F , s

20

f G

V

DS

380µs PULSE WIDTH

0

0 20406080100

ID, Drain-to-Source Current (A)

Fig 4. Typical Forward Transconductance

TJ = 25°C

TJ = 175°C

= 10V

Vs. Drain Current

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IRF4104S/LPbF

5000

4000

) F p

( e

3000

c n a

t

i c a p

2000

a C

, C

1000

0

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

gs

gd

ds

Ciss

Coss

Crss

+ Cgd, C

+ C

iss

C

rss

C

oss

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000.0

) A

( t

100.0

n e

r

r u

C n

i a

r

10.0

D e

s

r e v e

R ,

D S

I

TJ = 175°C

TJ = 25°C

1.0

0.1

0.2 0.6 1.0 1.4 1.8

VSD, Source-toDrain Voltage (V)

20

SHORTED

ds

gd

ID= 75A

) V

(

16

e g a

t

l o V

12

e c

r u o S

o

8

t

e

t a

G ,

S

4

G

V

0

0 20406080100

VDS= 32V

VDS= 20V

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

V

GS

= 0V

10000

) A

( t

1000

n e

r

r u

C e

c

r u o S

o

t

n

i a

r D ,

D

I

100

10

Tc = 25°C Tj = 175°C Single Pulse

1

0 1 10 100 1000

OPERATION IN THIS AREA LIMITED BY RDS(on)

V

, Drain-toSource Voltage (V)

DS

100µsec

1msec

10msec

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

4 www.irf.com

IRF4104S/LPbF

τ

120

LIMITED BY PACKAGE

100

) A

(

80

t n e

r

r u

60

C n

i a

r D

,

40

D

I

20

0

25 50 75 100 125 150 175

TC , Case Temperature (°C)

Fig 9. Maximum Drain Current Vs.

Case Temperature

10

2.0

e c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D

,

) n o

( S D

R

ID = 75A

V

= 10V

GS

1.5

) d e z

i

l a

m

r o

N

(

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 10. Normalized On-Resistance

Vs. Temperature

)

C

1

J h

t

Z (

e s n o p s e

R l a

m

r e h T

0.001

D = 0.50

0.20

R

0.1

0.01

0.10

0.05

0.02

0.01

τ

J

τ

J

τ

1

τ

1

Ci= τi/Ri

1

R

1

τ

SINGLE PULSE ( THERMAL RESPONSE )

1E-006 1E-005 0.0001 0.001 0.01 0.1

R

2

3

R

2

τ

2

Ri (°C/W) τi (sec)

R

3

τ

C

τ

0.371 0.000272

3

0.337 0.001375

τ

3

0.337 0.018713

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com 5

IRF4104S/LPbF

A

15V

L

D.U.T

I

AS

Ω

0.01

t

p

R

20V

V

DS

G

GS

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

I

AS

Fig 12b. Unclamped Inductive Waveforms

Q

G

DRIVER

+

-

V

DD

500

) J

m

( y

g

r

400

e n E

e h c

300

n a

l a v A

e s

200

l u P

e

l g n

i

100

S

, S A

E

0

25 50 75 100 125 150 175

I

TOP 11A 16A BOTTOM 75A

Starting TJ, Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

D

10 V

Q

GS

V

G

Fig 13a. Basic Gate Charge Waveform

Current Regulator

Same Type as D.U.T.

.2µF

12V

V

GS

Fig 13b. Gate Charge Test Circuit

Q

GD

Charge

50KΩ

.3µF

D.U.T.

3mA

I

G

Current Sampling Resistors

4.0

) V

( e

g a

t

l o

3.0

V d

l o h s e

r h

t e

t a

2.0

G

) h

t

( S G

+

V

DS

-

V

1.0

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 250µA

TJ , Temperature ( °C )

D

Fig 14. Threshold Voltage Vs. Temperature

6 www.irf.com

IRF4104S/LPbF

1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs

100

) A

( t n e

r

r u

C

10

e h c n a

l a v A

1

0.1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02

0.01

0.05

0.10

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

avalanche pulsewidth, tav assuming ∆ Tj = 25°C due to

avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax

140

TOP Single Pulse

120

) J

m

(

100

y g

r e n E

80

e h c n

60

a

l a v A ,

40

R A

E

20

0

25 50 75 100 125 150 175

BOTTOM 1% Duty Cycle ID = 75A

Starting TJ , Junction Temperature (°C)

Fig 16. Maximum Avalanche Energy

Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T every part type.

2. Safe operation in Avalanche is allowed as long asT not exceeded.

. This is validated for

jmax

3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.

4. P

avalanche pulse.

= Average power dissipation per single

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ∆T = Allowable rise in junction temperature, not to exceed

T

(assumed as 25°C in Figure 15, 16).

jmax

t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see figure 11)

thJC

P

= 1/2 ( 1.3·BV·Iav) = DT/ Z

D (ave)

I

2DT/ [1.3·BV·Zth]

av =

E

AS (AR)

= P

·f

av

D (ave)·tav

thJC

www.irf.com 7

is

IRF4104S/LPbF





Reverse Recovery Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied Voltage

+

-

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

R

D.U.T.

D

+

V

DD

-

V

DS

V

GS

R

G

10V

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

V

DS

90%

10% V

GS

t

d(on)tr

t

d(off)tf

Fig 18b. Switching Time Waveforms

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TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

IRF4104S/LPbF

TO-220AB Part Marking Information

EXAMPLE : THIS IS AN IRF 1010

Note: "P" in assembly line position

LOT CODE 1789 ASS EMBL ED ON WW 19, 2000 IN THE ASSEMBLY LINE "C"

indi cates "L ead - F ree"

INTE RNATIONAL

RECT IFIER

LOGO

ASSEMBLY LOT CODE

TO-220AB package is not recommended for Surface Mount Application

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/datasheets/data/auirf4104.pdf

2. For the most current drawing please refer to IR website at

http://www.irf.com/package/

www.irf.com 9

PART NUMBER

DAT E CODE YEAR 0 = 2000 WEEK 19 LINE C

IRF4104S/LPbF

2

Pak (TO-263AB) Package Outline

D

Dimensions are shown in millimeters (inches)

D2Pak (TO-263AB) Part Marking Information

THIS IS AN IRF530S WITH LOT CODE 8024

ASSE MBLE D ON WW 02, 2000 IN THE AS SE MBLY LINE "L"

INTER NATIONAL

RECTIF IER

LOGO

ASSEMBLY LOT CODE

F530S

OR

INTER NATIONAL

RECTIF IER

LOGO

ASSEMBLY LOT CODE

F530S

PART NUMBER

DAT E CODE P = DE S IGN ATE S LE AD - F RE E

PRODUCT (OPTIONAL) YE AR 0 = 2000 WEEK 02 A = AS S EMB LY S I TE CODE

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/datasheets/data/auirf4104.pdf

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

10 www.irf.com

PART NUMBER

DAT E CODE YEAR 0 = 2000 WE EK 02 LINE L

TO-262 Package Outline

Dimensions are shown in millimeters (inches)

IRF4104S/LPbF

TO-262 Part Marking Information

THIS IS AN IRL3103L

EXAMPLE:

LOT CODE 1789 ASSE MBL ED ON WW 19, 1997 IN THE ASSEMBLY LINE "C"

Note: "P" in assembly line pos it ion i ndicates "L ead-F ree"

INTE RNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

OR

INTE RNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

www.irf.com 11

PART NUMBER

DATE CODE YEAR 7 = 1997 WEEK 19 LINE C

PART NUMBER

DATE CODE

P = D ES IGNAT E S L EAD -FR E E

PRODUCT (OPTIONAL)

YEAR 7 = 1997 WE EK 19 A = ASSEMBLY SITE CODE

IRF4104S/LPbF

D2Pak Tape & Reel Information

TRR

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

FEED DI RECTION

TRL

FEED DI RECTION

1.85 (.073)

1.65 (.065)

10.90 (.429)

10.70 (.421)

11.60 (.457)

11.40 (.449)

16.10 (.634)

15.90 (.626)

1.60 (.063)

1.50 (.059)

1.75 (.069)

1.25 (.049)

15.42 (.609)

15.22 (.601)

0.368 (.0145)

0.342 (.0135)

24.3 0 (.95 7)

23.9 0 (.94 1)

4.72 (.136)

4.52 (.178)

13.50 (.532)

12.80 (.504)

330.00 (14.173) MAX.

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

27.40 (1.079)

23.90 ( .941)

4

26.40 (1.039)

24.40 (.961)

3

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by T

RG = 25Ω, I

, starting TJ = 25°C, L = 0.04mH

Jmax

= 75A, VGS =10V. Part not

AS

recommended for use above this value.

 Pulse width ≤ 1.0ms; duty cycle ≤ 2%.  C

eff. is a fixed capacitance that gives the

oss

same charging time as C from 0 to 80% V

DSS

.

oss

while V

DS

is rising

 Limited by T

avalanche performance.

 This value determined from sample failure population. 100%

tested to this value in production.

 This is only applied to TO-220AB pakcage.  This is applied to D

4 or G-10 Material). For recommended footprint and soldering

techniques refer to application note #AN-994.

, see Fig.12a, 12b, 15, 16 for typical repetitive

Jmax

TO-220AB package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

60.00 (2. 362) MIN.

30.40 (1.197) MA X.

4

2

Pak, when mounted on 1" square PCB (FR-

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 07/2010

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