Datasheet IRF3711ZPbF, IRF3711ZSPbF, IRF3711ZLPbF Datasheet (IOR)

查询IRF3711ZLPBF供应商

Applications

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l Lead-Free

Benefits

l Low R l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage

and Current

DS(on)

at 4.5V V

GS

V

DSS

20V

TO-220AB

IRF3711Z

PD - 95530

IRF3711ZPbF

IRF3711ZSPbF

IRF3711ZLPbF

HEXFET® Power MOSFET

R

DS(on)

IRF3711ZS

6.0m

D2Pak

max

:

Qg

16nC

TO-262

IRF3711ZL

Absolute Maximum Ratings

Parameter Units

V

DS

V

GS

I

@ TC = 25°C

D

@ TC = 100°C

I

D

I

DM

PD @TC = 25°C

P

@TC = 100°C

D

T

J

T

STG

Drain-to-Source Voltage V

Gate-to-Source Voltage

Continuous Drain Current, V

Pulsed Drain Current

Maximum Power Dissipation W

Maximum Power Dissipation

Linear Derating Factor W/°C Operating Junction and °C

Storage Temperature Range

Soldering Temperature, for 10 seconds

Mounting Torque, 6-32 or M3 screw

c

Thermal Resistance

Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

R

JA

θ

Notes  through  are on page 12

Junction-to-Case

Case-to-Sink, Flat Greased Surface

Junction-to-Ambient

Junction-to-Ambient (PCB Mount)

i

fi

@ 10V

GS

@ 10V

GS

gi

Max.

20

± 20

92

h

65

h

380

79

40

0.53

-55 to + 175

300 (1.6mm from case)

f

10 lbf

y

in (1.1Nym)

––– 1.89 °C/W

0.50 –––

––– 62

––– 40

A

www.irf.com 1

7/20/04

IRF3711Z/S/LPbF

/

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

BV

DSS

∆ΒV

DSS

R

DS(on)

V

GS(th)

∆V

GS(th)

I

DSS

I

GSS

gfs Forward Transconductance 46 ––– ––– S

Q

g

Q

gs1

Q

gs2

Q

gd

Q

godr

Q

sw

Q

oss

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

Drain-to-Source Breakdown Voltage 20 ––– ––– V

∆T

Breakdown Voltage Temp. Coefficient ––– 0.013 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 4.8 6.0

––– 5.9 7.3

Gate Threshold Voltage 1.55 2.0 2.45 V

∆T

Gate Threshold Voltage Coefficient ––– -5.6 ––– mV/°C

J

Drain-to-Source Leakage Current ––– ––– 1.0 µA

––– ––– 150

Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

Total Gate Charge ––– 16 24

Pre-Vth Gate-to-Source Charge ––– 4.6 –––

Post-Vth Gate-to-Source Charge ––– 1.4 ––– nC

Gate-to-Drain Charge ––– 5.3 –––

Gate Charge Overdrive ––– 4.7 ––– See Fig. 16

Switch Charge (Q

gs2

+ Qgd)

––– 6.7 –––

Output Charge ––– 9.5 ––– nC

Turn-On Delay Time ––– 12 –––

Rise Time ––– 16 –––

Turn-Off Delay Time ––– 15 ––– ns

Fall Time ––– 5.4 –––

Input Capacitance ––– 2150 –––

Output Capacitance ––– 680 ––– pF

Reverse Transfer Capacitance ––– 320 –––

VGS = 0V, ID = 250µA

Reference to 25°C, I

mΩ

V

= 10V, ID = 15A

GS

V

= 4.5V, ID = 12A

GS

= VGS, ID = 250µA

V

DS

V

= 16V, VGS = 0V

DS

V

= 16V, VGS = 0V, TJ = 125°C

DS

VGS = 20V

V

= -20V

GS

= 10V, ID = 12A

V

DS

= 10V

V

DS

V

= 4.5V

GS

I

= 12A

D

V

= 10V, VGS = 0V

DS

V

= 10V, VGS = 4.5V

DD

ID = 12A

Clamped Inductive Load

V

= 0V

GS

V

= 10V

DS

ƒ = 1.0MHz

Conditions

= 1mA

D

e

Avalanche Characteristics

E

AS

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

c

Repetitive Avalanche Energy

d

c

Parameter Units

Typ.

–––

Max.

130

12

7.9

mJ

A

mJ

Diode Characteristics

Parameter Min. Typ. Max. Units

h

I

S

Continuous Source Current ––– –––

(Body Diode) A

I

SM

V

SD

t

rr

Q

rr

Pulsed Source Current ––– ––– 380

(Body Diode)

c

Diode Forward Voltage ––– ––– 1.0 V

Reverse Recovery Time ––– 16 24 ns

Reverse Recovery Charge ––– 6.0 9.0 nC

92

MOSFET symbol

showing the integral reverse

p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V

= 25°C, IF = 12A, VDD = 10V

T

J

di/dt = 100A/µs

Conditions

D

G

S

e

2 www.irf.com

IRF3711Z/S/LPbF

1000

VGS

TOP 10V

D

100

10

9.0V

7.0V

5.0V

4.5V

4.0V

3.5V BOTTOM 3.0V

3.0V

60µs PULSE WIDTH

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

Tj = 25°C

1

0.1 1 10

VDS, Drain-to-Source Voltage (V)

1000

)

Α

(

t n e

r

100

u C e

c

r u o S

o

t

-

10

n

i a

r D

,

D

I

TJ = 25°C

V

DS

TJ = 175°C

= 10V

60µs PULSE WIDTH

1

2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, Gate-to-Source Voltage (V)

1000

VGS

TOP 10V

100

D

9.0V

7.0V

5.0V

4.5V

4.0V

3.5V BOTTOM 3.0V

10

3.0V

60µs PULSE WIDTH

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

Tj = 175°C

1

0.1 1 10

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

2.0

e c n a

t s

i s e

R n O

)

e

d

c

e

r

z

u

i

l

o

a

S

-

m

o

r

t

o

n

N

i

( a

r D

,

) n o

( S D

R

ID = 30A

V

= 10V

GS

1.5

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

www.irf.com 3

IRF3711Z/S/LPbF

) F p

( e

c n a

t

i c a p a

C ,

C

10000

1000

100

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

+ Cgd, C

gs

gd

+ C

ds

Ciss

Coss

Crss

gd

iss

C

rss

C

oss

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

1000.0

) A

( t

100.0

n e

r

r u

C n

i a

r

10.0

D e

s

r e v e

R ,

D S

I

TJ = 175°C

1.0

0.1

0.0 0.5 1.0 1.5 2.0 2.5

VSD, Source-toDrain Voltage (V)

TJ = 25°C

SHORTED

ds

V

GS

= 0V

12

) V

( e

g a

t

l o V

e c

r u o S

o

t

e

t a

G ,

V

ID= 12A

10

8

6

4

S G

2

0

0 5 10 15 20 25 30 35 40

Q

VDS= 15V

VDS= 10V

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

10000

) A

( t

1000

n e

r

r u

C e

c

r u

100

o S

o

t

n

i a

r D

10

,

D

I

Tc = 25°C Tj = 175°C Single Pulse

1

0 1 10 100

OPERATION IN THIS AREA LIMITED BY RDS(on)

V

, Drain-toSource Voltage (V)

DS

100µsec

1msec

10msec

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

4 www.irf.com

IRF3711Z/S/LPbF

τ

100

LIMITED BY PACKAGE

80

) A

( t n e

60

r

r u

C n

i a

r

40

D ,

D

I

20

0

25 50 75 100 125 150 175

TC , Case Temperature (°C)

Fig 9. Maximum Drain Current vs.

Case Temperature

10

2.4

) V

(

2.0

e g a

t

l o V

d

l

1.6

o h s e

r h

t

1.2

e

t a

G

) h

t

(

0.8

S G

V

0.4

-75 -50 -25 0 25 50 75 100 125 150 175 200

ID = 250µA

TJ , Temperature ( °C )

Fig 10. Threshold Voltage vs. Temperature

)

C

1

0.1

0.01

D = 0.50

0.20

0.10

0.05

0.02

0.01

SINGLE PULSE ( THERMAL RESPONSE )

τ

J

τ

J

τ

1

τ

1

Ci= τi/Ri

R

1

R

1

R

2

3

R

2

τ

2

τ

2

Ri (°C/W) τi (sec)

R

3

τ

0.894 0.000306

C

τ

3

τ

0.600 0.001019

3

0.401 0.006662

Notes:

1. Duty Factor D = t1/t2

J h

t

Z (

e s n o p s e

R l a

m

r e h T

2. Peak Tj = P dm x Zthjc + Tc

0.001

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com 5

IRF3711Z/S/LPbF

A

)

0.02

Ω

( e

c n a

t s

i s e

R n O e

c

r

0.01

u o S

o

t

n

i a

r D

,

) n o

(

S D

0.00

R

2.0 4.0 6.0 8.0 10.0

ID = 15A

TJ = 125°C

TJ = 25°C

VGS, Gate-to-Source Voltage (V)

Fig 12. On-Resistance Vs. Gate Voltage

15V

DRIVER

+

-

V

R

V

20V

V

DS

G

GS

L

D.U.T

I

AS

0.01

t

p

Ω

Fig 13a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

DD

600

) J

m

( y

500

g

r e n E

e

400

h c n a

l a

300

v A

e s

l u

200

P e

l g n

i S

100

, S A

E

0

25 50 75 100 125 150 175

I

TOP

8.6A

BOTTOM

Starting TJ, Junction Temperature (°C)

Fig 13c. Maximum Avalanche Energy

vs. Drain Current

V

DS

D.U.T

V

GS

Pulse Width < 1µs

Duty Factor < 0.1%

Fig 14a. Switching Time Test Circuit

V

DS

90%

7.3A

L

D

V

DD

D

12A

+

-

10%

V

GS

I

AS

Fig 13b. Unclamped Inductive Waveforms

t

d(on)

r

Fig 14b. Switching Time Waveforms

t

d(off)

t

f

6 www.irf.com

IRF3711Z/S/LPbF





Reverse Recovery Current

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied Voltage

+

-

Period

P.W.

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Current Regulator

Same Type as D.U.T.

Vds

Id

Vgs

50KΩ

12V

.2µF

.3µF

D.U.T.

+

V

DS

-

Vgs(th)

V

GS

3mA

I

G

Current Sampling Resistors

Fig 16. Gate Charge Test Circuit

I

D

Qgs1

Qgs2 Qgd Qgodr

Fig 17. Gate Charge Waveform

www.irf.com 7

IRF3711Z/S/LPbF

)

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R MOSFET, but these conduction losses are only about one half of the total losses.

Power losses in the control switch Q1 are given by;

P

= P

loss

P

loss

conduction

This can be expanded and approximated by;

= I

()

rms

⎛ ⎜

+ I ×

⎝

+ Qg× Vg× f

()

Q

⎛

+

⎝

This simplified loss equation includes the terms Q and Q

charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q Fig 16.

the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I gins to change. Minimizing Q reducing switching losses in Q1.

put capacitance of the MOSFET during every switching cycle. Figure A shows how Q parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.

which are new to Power MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the out-

oss

+ P

2

× R

ds(on )

Q

gd

× Vin× f

i

g

oss

×Vin× f

2

at which time the drain voltage be-

dmax

switching

⎞ ⎟

⎠

⎞ ⎠

and Q

gs1

+ P

+ I ×

+ P

drive

⎛

Q

gs2

⎜

i

⎝

g

, can be seen from

gs2

is a critical factor in

gs2

is formed by the

oss

of the

ds(on)

output

× Vin× f

Synchronous FET

The power loss equation for Q2 is approximated

by;

P

= P

loss

P

loss

+ Qg× Vg× f

+

conduction

= I

rms

()

⎛

Q

⎜ ⎝

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R

portant characteristic; however, once again the im-

⎞ ⎟

portance of gate charge must not be overlooked since

⎠

it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q verse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

gs2

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Q potential for Cdv/dt turn on.

Figure A: Q

+ P

2

× R

ds(on)()

oss

×Vin× f

2

must be minimized to reduce the

gs1

Characteristic

oss

drive

*

+ P

output

⎞

+ Qrr× Vin× f

(

⎠

ds(on)

oss

is an im-

and re-

8 www.irf.com

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

IRF3711Z/S/LPbF

10.54 (.415)

2.87 (.113)

2.62 (.103)

15.24 (.600)

14.84 (.584)

14.09 (.555)

13.47 (.530)

1.40 (.055)

3X

1.15 (.045)

2.54 (.1 00)

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14 .5M, 1982. 3 OUTLINE C ONFORMS TO JEDE C OUTLINE TO-220AB.

2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

10.29 (.405)

4

1 2 3

2X

3.78 (.149)

3.54 (.139)

- A -

6.47 (.255)

6.10 (.240)

1.15 (.045) MIN

4.06 (.160)

3.55 (.140)

0.93 (.037)

3X

0.69 (.027)

0.36 (.014 ) M B A M

4.69 (.185)

4.20 (.165)

- B -

1.32 (.052)

1.22 (.048)

2.92 (.115)

2.64 (.104)

HEXFET

1- GATE 2- DRAIN 3- SOURCE 4- DRAIN

3X

LEAD ASSIG NMENTS

LEAD ASSIGNMENTS 1 - GATE 2 - DRA IN 3 - SOURC E 4 - DRA IN

0.55 (.022)

0.46 (.018)

TO-220AB Part Marking Information

IGBTs, CoPACK

1- GATE 2- COLLECTO R 3- EMITTER 4- COLLECTO R

EXAMPLE:

T HIS IS AN IRF 1010

LOT CODE 1789 ASS EMBL ED ON WW 19, 1997 IN THE ASSEMBLY LINE "C"

Note: "P" in assembly line position indicates "Lead-Free"

INTERNATIONAL

RE CTIFIER

LOGO

AS S E MB LY LOT CODE

PART NUMBER

DATE CODE YEAR 7 = 1997 WEEK 19 LINE C

www.irf.com 9

IRF3711Z/S/LPbF

2

Pak Package Outline

D

Dimensions are shown in millimeters (inches)

D2Pak Part Marking Information (Lead-Free)

T H IS IS AN IR F 530S WIT H LOT CODE 8024

ASS EMB L ED ON WW 02, 2000 IN T HE AS SE MB L Y L IN E "L"

No te: "P" in as sem bly line pos ition in dicates "L ead-F ree"

INT ER NAT ION AL

R E CT IFIE R

LOGO

AS SE MB LY LOT CODE

F 530S

PART NUMB ER

DATE CODE YEAR 0 = 2000 WEE K 02 LINE L

OR

INT ER N AT ION AL

R E CTIF IE R

LOGO

AS SE MB LY LOT CODE

F 530S

10 www.irf.com

PART NUMBE R

DATE CODE

P = D E S IGNAT E S LE AD-F RE E

PRODUCT (OPTIONAL)

YEAR 0 = 2000 WEE K 02

A = AS S E MB L Y S IT E CO DE

TO-262 Package Outline

IRF3711Z/S/LPbF

IGBT

1- GATE

2- COLLECTOR

3- EMITTER

TO-262 Part Marking Information

EXAMPLE:

TH IS IS AN IRL 3103L LOT CODE 1789 ASS EMBL ED ON WW 19, 1997 IN THE ASSEMBLY LINE "C"

Note: "P" in ass embly line position indicates "Lead-Free"

INTERNATIONAL

RECTIFIER

LOGO

AS S E MB L Y LOT CODE

PART NUMBER

DATE CODE YEAR 7 = 1997 WEEK 19 LINE C

OR

INTERNATIONAL

RECTIFIER

LOGO

AS S E MB L Y LOT CODE

www.irf.com 11

PART NUMBER

DATE CODE P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

YE AR 7 = 1997 WEEK 19

A = ASSEMBLY SITE CODE

IRF3711Z/S/LPbF

D2Pak Tape & Reel Infomation

TRR

FEED DIRECTION

TRL

FEED DI RECTION

1.85 (.073)

1.65 (.065)

10.90 (. 429)

10.70 (. 421)

4.10 (.161)

3.90 (.153)

1.60 (.063)

1.50 (.059)

11.60 (.457)

11.40 (.449)

16.10 (.634)

15.90 (.626)

1.60 (.063)

1.50 (.059)

1.75 (.069)

1.25 (.049)

15.42 (.609)

15.22 (.601)

0.368 (.0145)

0.342 (.0135)

24.30 (.957)

23.90 (.941)

4.72 (.136)

4.52 (.178)

13.50 (.532)

12.80 (.504)

330.00 (14.173) MAX.

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

27.40 (1.079)

23.90 (.941)

4

26.40 (1.039)

24.40 (.961 )

3

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature.

 Starting T

I

AS

= 25°C, L = 1.8mH, RG = 25Ω,

J

= 12A.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

 This is only applied to TO-220AB pakcage.  This is applied to D

4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994.

 Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 30A.

 R

is measured at TJ approximately 90°C

θ

TO-220AB package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

60.00 (2.362) MIN.

30.40 (1.197) MAX.

4

2

Pak, when mounted on 1" square PCB (FR-

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 7/04

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Datasheet IRF3711ZPbF, IRF3711ZSPbF, IRF3711ZLPbF Datasheet (IOR)

Specifications and Main Features

Frequently Asked Questions

User Manual