Datasheet irf3705ns Datasheet

PD - 9.1502B

IRL3705NS/L

l Logic-Level Gate Drive l Advanced Process Technology

l Surface Mount (IRL3705NS) l Low-profile through-hole (IRL3705NL) l 175°C Operating Temperature l Fast Switching l Fully Avalanche Rated

Description

Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.

2

The D

Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The

2

D

Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL3705NL) is available for lowprofile applications.

G

HEXFET® Power MOSFET

2

D Pa k

D

S

V

R

DS(on)

I

TO-262

= 55V

DSS

= 0.01Ω

= 89A

D

Absolute Maximum Ratings

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 89 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 63 A I

DM

PD @TA = 25°C Power Dissipation 3.8 W PD @TC = 25°C Power Dissipation 170 W

V

GS

E

AS

I

AR

E

AR

dv/d t Peak Diode Recovery dv/dt  5.0 V/ns T

J

T

STG

Pulsed Drain Current  310

Linear Derating Factor 1.1 W/°C Gate-to-Source Voltage ± 16 V Single Pulse Avalanche Energy 340 mJ Avalanche Current 46 A Repetitive Avalanche Energy 1.7 mJ

Operating Junction and -55 to + 175 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Thermal Resistance

Parameter Typ. Max. Units

R

θJC

R

θ JA

Junction-to-Case ––– 0.90 Junction-to-Ambient ( PCB Mounted,steady-state)** ––– 40

°C/W

°C

8/25/97

IRL3705NS/L

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions

V

(BR)DSS

∆V

(BR)DSS

R

DS(on)

V

GS(th)

g

fs

I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

S

C

iss

C

oss

C

rss

Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA

/∆T

Breakdown Voltage Temp. Coefficient ––– 0.056 ––– V/°C Reference to 25°C, ID = 1mA

J

= 10V, ID = 46A 

GS

= 5.0V, ID = 46A 

GS

Static Drain-to-Source On-Resistance

––– ––– 0.010 V ––– ––– 0.012 Ω V

––– ––– 0.018 VGS = 4.0V, ID = 39A  Gate Threshold Voltage 1.0 ––– 2 .0 V VDS = VGS, ID = 250µA Forward Transconductance 50 ––– ––– S VDS = 25V, ID = 46A

Drain-to-Source Leakage Current

––– ––– 25 V

––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V

A

nA

= 55V, VGS = 0V

DS

= 16V

V

GS

Total Gate Charge ––– ––– 98 ID = 46A Gate-to-Source Charge ––– ––– 19 nC VDS = 44V Gate-to-Drain ("Miller") Charge ––– ––– 49 VGS = 5.0V, See Fig. 6 and 13  Turn-On Delay Time ––– 12 ––– VDD = 28V Rise Time ––– 140 ––– ID = 46A Turn-Off Delay Time ––– 3 7 ––– RG = 1.8Ω, VGS = 5.0V

ns

Fall Time ––– 78 ––– RD = 0.59Ω, See Fig. 10  Internal Source Inductance 7.5

––– –––

Between lead,

nH

and center of die contact Input Capacitance ––– 3600 ––– VGS = 0V Output Capacitance ––– 870 ––– pF VDS = 25V Reverse Transfer Capacitance ––– 320 ––– ƒ = 1.0MHz, See Fig. 5

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. ( See fig. 11 )

 V

DD

RG = 25Ω, I

 I

SD

TJ ≤ 175°C

** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.

Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode) 

––– –––

89

310

showing the

A

p-n junction diode. Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 46A, VGS = 0V  Reverse Recovery Time ––– 94 140 ns TJ = 25°C, IF = 46A Reverse Recovery Charge ––– 290 440 nC di/dt = 100A/µs Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

 Pulse width ≤ 300µs; duty cycle ≤ 2%.

= 25V, starting TJ = 25°C, L = 320µH

= 46A. (See Figure 12)

AS

≤ 46A, di/dt ≤ 250A/µs, V

DD

≤ V

(BR)DSS

 Uses IRL3705N data and test conditions  Calculated continuous current based on maximum allowable

,

junction temperature; for recommended current-handling of the package refer to Design Tip # 93-4



D

G

S

IRL3705NS/L

1000

VGS TOP 15V 12V 10V

8.0V

6.0V

4.0V

3.0V BOTT OM 2.5V

100

10

D

I , Drain- to-S o urce C u rrent ( A)

2.5V 20µs PULSE WIDTH

T = 25°C

1

0.1 1 10 100

V , Dra in-to-So urc e V olta ge (V )

DS

J

Fig 1. Typical Output Characteristics

1000

VGS TOP 15V 12V 10V

8.0V

6.0V

4.0V

3.0V BOTT OM 2.5V

100

10

D

I , Drain- to-S o urce C u rrent ( A)

2.5V

20µs PULSE WIDTH T = 175°C

A

1

0.1 1 10 100

V , Dra in-to-So urc e V olta ge (V )

DS

J

A

Fig 2. Typical Output Characteristics

3.0

I = 77A

D

T = 25°C

J

T = 175°C

100

10

D

I , Dr a in -to- So u rce C urr en t (A)

1

2.0 3.0 4.0 5.0 6.0 7.0 8.0

V , Ga te-to-Source Voltage (V)

GS

J

V = 25 V

DS

20µs PULSE WIDTH

Fig 3. Typical Transfer Characteristics

2.5

2.0

1.5

(No rm a lized)

1.0

0.5

DS(on)

R , D rain -to-S ou rc e O n R e si stan ce

A

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

T , Ju nc tion Temperature (°C )

J

V = 10V

GS

A

Fig 4. Normalized On-Resistance

Vs. Temperature

IRL3705NS/L

6000

5000

4000

3000

2000

C, C apac itance (pF)

1000

0

1 10 100

V = 0V, f = 1MHz

GS

C = C + C , C SHORTED

iss gs gd ds

C = C

rss gd

C

C = C + C

iss

oss ds g d

C

oss

C

rs s

V , Drai n-to -Sourc e V olt ag e (V )

DS

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000

15

I = 46A

V , G ate-to -S ou rce V oltage (V )

12

9

6

3

GS

D

V = 44V

DS

V = 28V

DS

FOR TEST CIRCUIT

A

0

0 20 40 60 80 100 120 140

Q , Total Ga te Ch arg e (nC)

G

SEE FIG URE 1 3

A

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

O PER ATION IN T HIS A R E A LI MITED BY R

DS(on)

100

T = 175°C

J

T = 25°C

J

SD

I , Rev ers e Dr ain C u rren t (A)

10

0.4 0.8 1.2 1.6 2.0 2.4 2.8

V , Source-to-Drain Voltage (V)

SD

V = 0V

Fig 7. Typical Source-Drain Diode

Forward Voltage

GS

10µs

100

100µs

10

D

I , D rain C u rren t (A)

T = 25°C

C

T = 175°C

J

Single Pulse

A

1

1 10 100

V , Drain-to-So urc e Vo ltag e (V)

DS

1ms

10ms

A

Fig 8. Maximum Safe Operating Area

IRL3705NS/L

+

-

100

LIMITED BY PACKAGE

80

60

40

D

I , Drain Current (A)

20

0

25 50 75 100 125 150 175

T , Case Temperature ( C)

C

°

Fig 9. Maximum Drain Current Vs.

Case Temperature

1

R

V

DS

V

GS

R

G

D

D.U.T.

5.0V

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

Fig 10a. Switching Time Test Circuit

V

DS

90%

10% V

GS

t

d(on)tr

t

d(off)tf

Fig 10b. Switching Time Waveforms

V

DD

D = 0.50

thJC

0.20

0.10

0.1

0.05

0.02

Thermal Response (Z )

0.01

0.00001 0.0001 0.001 0.01 0.1 1

SINGLE PULSE

(THERMAL RESPONSE)

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

J DM thJC C

t , Rectangular Pulse Duration (sec)

1

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1 2

P

DM

t

1

t

2

IRL3705NS/L

15V

DRIVER

+

-

V

DD

R

V

G

10V

DS

L

D.U.T

I

AS

Ω

t

0.01

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

800

600

400

A

200

AS

V = 25V

E , S in gle Pulse A valanche Energ y (m J)

DD

0

25 50 75 100 125 150 175

Starting T , Junction Temperature (°C)

J

I TOP 19A 33A BOTTOM 46 A

D

A

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

I

AS

Fig 12b. Unclamped Inductive Waveforms

Q

G

5.0 V

Q

GS

V

G

Q

GD

Charge

Current Regulator

Same Type as D.U.T.

12V

.2µF

V

GS

Fig 13b. Gate Charge Test CircuitFig 13a. Basic Gate Charge Waveform

50KΩ

.3µF

D.U.T.

3mA

I

G

Current Sampling Resistors

I

+

V

DS

-

D

IRL3705NS/L

+

-

Peak Diode Recovery dv/dt Test Circuit

+





D.U.T

-

R

G

Driver Gate Drive

P.W.

+

Circuit Layout Considerations

• Low Stray Inductance



• Ground Plane

• Low Leakage Inductance Current Transformer

-

• dv/dt controlled by R

• Driver same type as D.U.T.

controlled by Duty Factor "D"

• I

SD

• D.U.T. - Device Under Test

Period

-

D =



G

Period

P.W.

+

V

DD

VGS=10V

*

Reverse Recovery Current

Re-Applied Voltage

D.U.T. ISDWaveform

Body Diode Forward

Current

D.U.T. VDSWaveform

Inductor Curent

Ripple ≤ 5%

* V

= 5V for Logic Level Devices

GS

Diode Recovery

dv/dt

Body Diode Forward Drop

Fig 14. For N-Channel HEXFETS

di/dt

V

DD

I

SD

IRL3705NS/L

D2Pak Package Outline

10.54 (.415)

1.40 (.055) MAX.

1.78 (.070)

1.27 (.050)

1.40 (.055)

3X

1.14 (.045)

5.08 (.200)

NOTES: 1 DIMENSIONS AFTER SO LDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIME NSIONS DO NOT INCLUDE BURRS .

10.29 (.405)

- A 2

1 3

15.49 (.610)

14.73 (.580)

0.93 (.037)

3X

0.69 (.027)

0.25 (.010) M B A M

Part Marking Information

D2Pak

4.69 (.185)

4.20 (.165)

5.28 (.208)

4.78 (.188)

0.55 (.022)

0.46 (.018)

- B -

1.32 (.052)

1.22 (.048)

2.79 (.110)

2.29 (.090)

1.39 (.055)

1.14 (.045)

LEAD ASS IGNM ENT S 1 - GATE 2 - DRAIN 3 - SOURCE

10.16 (.400) RE F.

6.47 (.255)

6.18 (.243)

2.61 (.103)

2.32 (.091)

8.89 (.350) RE F.

MINIMUM RECOMMENDED FOOTP RINT

11.43 (.450)

8.89 (.350)

17.78 (.700)

3.81 (.150)

2.08 (.082) 2X

2.54 (.100) 2X

INTERNATIONAL RECTIFIER L OG O

AS SEMBLY LOT CO DE

F530S

9246

9B 1M

PART NUMBER

A

DATE CODE (YYW W) YY = YEAR WW = WEEK

Package Outline

TO-262 Outline

IRL3705NS/L

Part Marking Information

TO-262

IRL3705NS/L

Tape & Reel Information

D2Pak

TRR

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

1.60 (.063)

1.50 (.059)

0.368 (.0145)

0.342 (.0135)

FEED DIRECTION

1.85 (.073)

1.65 (.065)

TRL

10.90 (.429)

10.70 (.421)

FEED DIRECTION

13.5 0 (. 532 )

12.8 0 (. 504 )

330.0 0 (14.17 3) M AX .

NOT ES :

1. CO MFO RMS TO EIA -418.

2. CONTRO LLING DIMEN SION: MILLIME TER .

3. DIM E NS IO N MEASURE D @ HUB .

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

11.6 0 (.457 )

11.4 0 (.449 )

1.75 (.0 69 )

1.25 (.0 49 )

16.10 (.634)

15.90 (.626)

15.4 2 (.609 )

15.2 2 (.601 )

27.4 0 (1 .079)

23.9 0 (.9 41) 4

26.40 (1. 03 9)

24.40 (.961)

3

24.30 (.957)

23.90 (.941)

4.72 (.136)

4.52 (.178)

60.0 0 (2 .362) M IN .

30.4 0 (1 .197) M A X .

4

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http://www.irf.com/ Data and specifications subject to change without notice. 8 / 97