l Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
G
D
V
R
DS(on)
= 55V
DSS
= 11mΩ
ID = 85A
S
Description
Advanced HEXFET® Power MOSFETs from International
Rectifier utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 watts. The low thermal
resistance and low package cost of the TO-220 contribute
TO-220AB
to its wide acceptance throughout the industry.
Absolute Maximum Ratings
ParameterMax.Units
ID @ TC = 25°CContinuous Drain Current, VGS @ 10V85
ID @ TC = 100°CContinuous Drain Current, VGS @ 10V60A
I
DM
PD @TC = 25°CPower Dissipation180W
V
GS
I
AR
E
AR
dv/dtPeak Diode Recovery dv/dt 3.6V/ns
T
J
T
STG
Pulsed Drain Current 290
Linear Derating Factor1.2W/°C
Gate-to-Source Voltage ± 20V
Avalanche Current43A
Repetitive Avalanche Energy18mJ
Operating Junction and-55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds300 (1.6mm from case )
Mounting torque, 6-32 or M3 srew10 lbf•in (1.1N•m)
and center of die contact
Input Capacitance––– 3210 –––VGS = 0V
Output Capacitance–––690 –––VDS = 25V
Reverse Transfer Capacitance–––140 –––pFƒ = 1.0MHz, See Fig. 5
Single Pulse Avalanche Energy––– 1030250 mJI
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com5
Page 6
IRF1010NPbF
A
15V
DRIVER
+
V
DD
-
R
V
20V
V
DS
G
GS
L
D.U.T
I
AS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
500
TOP
400
300
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
255075100125150175
Starting T , Junction Temperature ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Current Regulator
Same Type as D.U.T.
I
°
D
18A
30A
43A
50KΩ
Q
G
V
GS
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
12V
Fig 13b. Gate Charge Test Circuit
.2µF
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
I
D
6www.irf.com
+
V
DS
-
Page 7
IRF1010NPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
V
GS
• dv/dt controlled by R
• ISD controlled by Duty Factor "D"
G
• D.U.T. - Device Under Test
+
V
DD
-
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D =
P. W .
Period
VGS=10V
[ ] ***
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
*** V
= 5.0V for Logic Level and 3V Drive Devices
GS
Fig 14. For N-channel HEXFET
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
®
power MOSFETs
V
DD
[ ]
I
[ ]
SD
www.irf.com7
Page 8
IRF1010NPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (. 113)
2.62 (. 103)
15.24 (.600)
14.84 (.584)
14.09 (. 555)
13.47 (. 530)
10.54 (.415)
10.29 (.405)
1 2 3
3.78 (.1 49)
3.54 (.1 39)
- A -
6.47 (.255)
6.10 (.240)
4
1.15 (.0 45)
MIN
4.06 ( .160)
3.55 ( .140)
4.69 (.1 85)
4.20 (.1 65)
- B -
1.32 (.052)
1.22 (.048)
LEAD ASSI GNMENTS
LEAD ASSIGNMENTS
HEXFET
1 -GATE 2 -DRAIN
1- GATE
3 -SOURCE
2- DRAIN
3- S OURCE
4 -DRAIN
4- DRAIN
IGBTs, C oPACK
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
0.93 (. 037)
3X
1.40 (.055)
3X
1.15 (.045)
2.54 (.1 00)
NOTES:
1 DIMENSION ING & TOLER ANC ING PER AN SI Y14 .5M, 1982. 3 OUTLIN E CONFO RMS TO J EDE C OUTLINE TO -220AB .
2 CONTROL LING D IMENSION : INC H 4 HEA TSINK & LEAD ME ASUREME NTS DO NOT INCLUDE BURRS.
2X
0.69 (. 027)
0.36 (.014) M B A M
0.55 (. 022)
3X
0.46 (. 018)
2.92 (. 115)
2.64 (. 104)
TO-220AB Part Marking Information
EXAMPLE:
T HIS IS AN IRF 1010
LOT CODE 1789
ASS EMBL E D ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E RN ATIONAL
RE CT IFIE R
LOGO
AS SE MB LY
LOT CODE
Data and specifications subject to change without notice.
This product has been designed and qualified for the automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
PAR T NU MBE R
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/04
8www.irf.com
Page 9
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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