Datasheet IR3821MPbF, IR3821MTRPbF Datasheet (IRF)

01/08/08

1

PD-60331

IR3821MPbF

HIGHLY INTEGRATED 7A

WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

Features

• Wide Input Voltage Range 2.5V to 21V

• Wide Output Voltage Range 0.6V to 12V

• Continuous 7A Load Capability

• 600kHz High Frequency Operation

• Programmable Over-Current Protection

• Programmable PGood Output

• Hiccup Current Limit

• Precision Reference Voltage (0.6V)

• Programmable Soft-Start

• Pre-Bias Start-up

• Thermal Protection

• Thermally Enhanced Package

• Small Size 5mmx6mm QFN

• Pb-Free (RoHS Compliant)

Fig. 1. Typical application diagram

Description

The IR3821 SupIRBuckTMis an easy-to-use, fully
integrated and highly efficient DC/DC regulator.
The onboard switching controller and MOSFETs
make the IR3821 a space-efficient solution,
providing accurate power delivery for low output
voltage applications.

The IR3821 operates from a single 4.5V to 14V
input supply and generates an output voltage
adjustable from 0.6V to 0.75*Vin at loads up to 7A.

A versatile regulator offering programmability of
startup time, power good threshold and current
limit, the IR3821’s fixed 600kHz switching
frequency allows the use of small external
components.

The IR3821 also features important protection
functions, such as Pre-Bias startup, hiccup
current limit and thermal shutdown to provide the
required system level security in the event of fault
conditions.

Applications

• Distributed Point-of-Loads

• Server and Workstations

• Embedded Systems

• Storage Systems

• DDR Applications

• Graphics Cards

• Game Consoles

• Computing Peripheral Voltage Regulators

SupIRBuck

TM

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PD-60331

IR3821MPbF

PACKAGE INFORMATION

5mm x 6mm POWER QFN

12

V

IN

11

SW

10

PGnd

15

AGnd

1

23

4

5

6

7

8

9

14

13

Vsns FB COMP AGnd AGnd SS OCSet

PGood

V

CC

V

C

HG

Fig. 2: Package outline (Top view)

W/C2θ

W/C35θ

o

PCBJ

o

JA

=

=

-

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to GND)

•VINSupply Voltage -0.3V to 24V

• Vcc Supply Voltage -0.3V to 16V

• Vc Supply Voltage -0.3V to 30V

• SW -0.3V to 30V

• PGood -0.3V to 16V

• Fb,COMP,SS,Vsns -0.3V to 3.5V

•OCSet 10mA

• AGnd to PGnd -0.3V to +0.3V

• Storage Temperature Range -65°C To 150°C

• Operating Junction Temperature Range -40°C To 150°C

• ESD Classification JEDEC, JESD22-A114

• Moisture Sensitivity Level JEDEC Level 3 @ 260

o

C

Caution: Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the

device. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum
Rating” conditions for extended periods may affect device reliability.

4000

PARTS

PER REEL

---------------

PARTS

PER TUBE

15

PIN COUNT

IR3821MTRPbF

PACKAGE

DESCRIPTION

M

PKG

DESIG

ORDERING INFORMATION

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PD-60331

IR3821MPbF

Block Diagram

Fig. 3. Simplified block diagram of the IR3821.

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PD-60331

IR3821MPbF

Pin Description

Pin Name Description

1 Vsns PGood sense pin. Use two external resistors to program the power

good threshold.

2 Fb Inverting input to the error amplifier. This pin is connected directly to the

output of the regulator via resistor divider to set the output voltage and
provide feedback to the error amplifier.

3 Comp Output of error amplifier.
4 AGnd Signal ground for internal reference and control circuitry.

5 AGnd Signal ground for internal reference and control circuitry.
6 SS/SD Soft start / shutdown. This pin provides user programmable soft-start

function. Connect an external capacitor from this pin to signal ground
(AGnd) to set the start up time of the output voltage. The converter can
be shutdown by pulling this pin below 0.3V.

7 OCSet Current limit set point. A resistor from this pin to SW pin will set the

current limit threshold.

8

V

CC

This pin provides biasing voltage for the internal blocks of the IC. It also
powers the low side driver. A minimum of 0.1uF, high frequency
capacitor must be connected from this pin to power ground (PGnd).

9 PGood Power Good status pin. Output is open collector. Connect a pull up

resistor from this pin to Vcc.

10 PGnd Power Ground. This pin serves as a separated ground for the MOSFET

drivers and should be connected to the system’s power ground plane.

11 SW Switch node. This pin is connected to the output inductor
12

V

IN

Input vo ltage connection pi n

13 HG This pin is connected to the high side Mosfet gate. Connect a small

capacitor from this pin to switch node (SW).

14

V

C

This pin powers the high side driver and must be connected to a voltage
higher than input voltage. A minimum of 0.1uF high frequency capacitor
must be connected from this pin to the power ground (PGnd).

15 AGnd Signal ground for internal reference and control circuitry.

Pins 4, 5 and 15 need to be connected together on system board.

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PD-60331

IR3821MPbF

Recommended Operating Conditions

Parameter Symbol Test Condition Min TYP MAX Units

Power Loss

Power Loss

P

loss

Vcc=Vin=12V, Vc=24V, Vo=1.8V,

I

o

=7A, L=1.0uH, Note3

2.1 W

MOSFET R

ds(on)

Top Switch R

ds(on)_Top

ID=6A, Tj(MOSFET)=25oC

10.5 13.40

Bottom Switch R

ds(on)_Bot

ID=6A, Tj(MOSFET)=25oC

10.5 13.40

mΩ

Reference Voltage

Feedback Voltage VFB 0.6 V

0oC<Tj<105oC -1.35 +1.35 % Accuracy

-40

o

C<Tj<105oC,

Note2

-1.5 +1.5 %

Supply Current

VCC Supply Current (Static)

I

CC(Static)

SS=0V, No Switching 10 13

VC Supply Current
(Static)

I

C(Static)

SS=0V, No Switching 4.5 7

VCC Supply Current
(Dynamic)

I

CC(Dynamic)

SS=3V, Vc=24V, Vcc=Vin=12V.

V

o

=1.8V, Io=0A

18 25

VC Supply Current
(Dynamic)

I

C(Dynamic)

SS=3V, Vc=24V, Vcc=Vin=12V.

V

o

=1.8V, Io=0A

18 25

mA

Under Voltage Lockout

VCC-Start-Threshold VCC_UVLO(R) Supply ramping up 4.0 4.4
VCC-Stop-Threshold VCC_UVLO(F) Supply ramping down 3.7 4.1
VCC-Hysteresis Supply ramping up and down 0.15 0.25 0.3
VC-Start-Threshold VC_UVLO(R) Supply ramping up 3.1 3.5
VC-Stop-Threshold VC_UVLO(F) Supply ramping down 2.85 3.25
VC-Hysteresis Supply ramping up and down 0.15 0.2 0.25

V

Electrical Specifications

Unless otherwise specified, these specification apply over Vin=Vcc=Vc=12V, 0oC<Tj(Ic)< 105oC.
Typical values are specified at T

a

= 25oC.

Symbol Definition Min Max Units

Vin Input Voltage 2.5 21
Vcc Supply Voltage 4.5 14
Vc Supply Voltage Vin + 5V 28
Vo Output Voltage 0.6 12

V

I

o

Note1

Output Current 0 7 A

Tj Junction Temperature -40 125

o

C

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PD-60331

IR3821MPbF

Note1: Continuous output current determined by input and ou tput voltag e s et ting a nd the the rm al environment.
Note2: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
Note3: Guaranteed by Design but not tested in production.

Parameter SYM Test Condition Min TYP MAX Units

Oscillator

Frequency FS

540 600 660 kHz

Ramp Amplitude V

ramp

Note3

1.25 V

Min Pulse Width D

min(ctrl)

Note3

80 ns

Max Duty Cycle D

max

Fb=0V 75 %

Error Amplifier

Input Bias Curr ent I

FB1

SS=3V -0.1 -0.5

Input Bias Curr ent I

FB2

SS=0V 20 35 50

Source/Sink Current I(source/Sink) 50 70 90

μA

Transconductance gm 1000 1300 1600

μmho

Soft Start/SD

Soft Start Current ISS SS=0V 15 20 28

μA

Shutdown Output
Threshold

SD 0.25 V

Power Good

Vsns Low Trip Point Vsns(trip) Vsns Ramping Down 0.35 0.38 0.41 V

Hysteresis PGood(Hys) 15 27.5 40 mV

PGood Output Low
Voltage

PG(voltage) I

PGood

=4mA 0.25 0.5 V

Input Bias Current Isns 0 0.3 1

μA

Over Current Protection

OCSET Current I

OCSET

15 20 26

Hiccup Current I

Hiccup

Note3

3

μA

Hiccup Duty Cycle Hiccup(duty)

I

Hiccup

/ I

SS

,

Note3

15 %

Thermal Shutdown

Thermal Shutdown
Threshold

Note3

140

Thermal Shutdown
Hysteresis

Note3

20

o

C

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PD-60331

IR3821MPbF

TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC)

Icc(static)

7.0

8.0

9.0

10.0

11.0

12.0

13.0

-40 -20 0 20 40 60 80 100 120

Temp[oC]

[mA]

Ic(static)

2.0

3.0

4.0

5.0

6.0

7.0

-40-200 20406080100120

Temp[oC]

[mA]

Icc(dynami c)

13.0

14.0

15.0

16.0

17.0

18.0

19.0

20.0

21.0

22.0

-40 -20 0 20 40 60 80 100 120

Temp[oC]

[mA]

Ic(dyn amic )

13.0

14.0

15.0

16.0

17.0

18.0

19.0

20.0

21.0

22.0

-40 -20 0 20 40 60 80 100 120

Temp[oC]

[mA]

Vfb

585.0

590.0

595.0

600.0

605.0

-40 -20 0 20 40 60 80 100 120

Temp[oC]

[mV]

Iss

15.0

17.0

19.0

21.0

23.0

25.0

27.0

-40-200 20406080100120

Temp[oC]

[uA ]

Transconductance

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

-40 -20 0 20 40 60 80 100 120

Temp[oC]

[mmho]

Iocset

15.0

16.0

17.0

18.0

19.0

20.0

21.0

22.0

23.0

24.0

25.0

26.0

-40 -20 0 20 40 60 80 100 120

Temp[oC]

[uA ]

01/08/08

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PD-60331

IR3821MPbF

Circuit Description

THEORY OF OPERATION

The IR3821 is a voltage mode PWM
synchronous regulator and operates wi th a fixed
600kHz switching frequency, allowing the use of
small external components.

The output voltage is set by feedback pin (Fb)
and the internal reference voltage (0.6V). These
are two inputs to error amplifier. The err or signal
between these two inputs is amplified and it is
compared to a fixed frequency linear sawtooth
ramp.

A trailing edge modulation is used for generating
fixed frequency pulses (PWM) which drives the
internal N-channel MOSFETs.

The internal oscillator circuit uses on-chip
circuitry, eliminating the need for external
components.

The IR3821 operates with single input voltage
from 4.5V to 14V allowing an e xtended operating
input voltage range.

The over-current protection is performed by
sensing current through the R

DS(on)

of low side
MOSFET. This method enhances the converter’s
efficiency and reduces cost by eliminating a
current sense resistor. The current limit is
programmable by using an external resistor.

Under-Voltage Lockout

The under-voltage lockout circuit monitors the
two input supplies (Vcc and Vc) and assures that
the MOSFET driver outputs remain in the off
state whenever the supply voltage drops below
set thresholds. Lockout occurs if Vcc or Vc fall
below 4.3V and 3.3V respectively. Normal
operation resumes once Vcc and Vc rise above
the set values.

Thermal Shutdown

Temperature sensing is provided inside the
IR3821. The trip threshold is typically set to
140

o

C. When trip threshold is exceeded, thermal
shutdown turns off both MOSFETs. Thermal
shutdown is not latched and automatic restart is
initiated when the sensed temperature drops
within the operating range. There is a 20

o

C

hysteresis in the thermal shutdown threshold.

Pre-Bias Startup

The IR3821 is able to start up into pre-charged
output, which prevents oscillation and
disturbances of the output voltage.

The output starts in asynchronous fashion and
keeps the synchronous MOSFET off until the fir st
gate signal for control MOSFET is generated.
Figure 4 shows a typical Pre-Bias condition at
start up.

Depending on system configuration, a specific
amount of output capacitors may be required to
prevent discharging the output voltage.

Fig. 4: Pre-Bias start up

Vo

Time

V

Pre-Bias Voltage

Shutdown

The output can be shutdown by pulling the soft­start pin below 0.3V. This can eas ily be done by
using an external small signa l transistor. During
shutdown both MOSFET drivers will be turned
off. Normal operation will resume by cycling soft
start pin.

Power Good

The IR3821 provides an open collector power
good signal which reports the status of the
output. The output is sensed through the
dedicated Vsns pin. The power good threshold
can be externally programmed using two external
resistors. The power good comparator is
internally set to 0.38V (typical).

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PD-60331

IR3821MPbF

Soft-Start

The IR3821 has programmable soft-start to
control the output voltage rise and limit the inrush
current during start-up.

To ensure correct start-up, the soft-start
sequence initiates when Vcc and Vc rise above
their threshold and generate the Power On
Ready (POR) signal. The soft-start function
operates by sourcing current to charge an
external capacitor to about 3V.

Initially, the soft -start function clamps the output
of error amplifier by injecting a current (40uA)
into the Fb pin and generates a voltage about

0.96V (40ux24K) across the negative input of
error amplifier (see figure 5).

The magnitude of the injected current is inve rsel y
proportional to the voltage at the soft-start pin. As
the soft-start voltage ramps up, the injected
current decreases linearly and so does the
voltage at negative input of error amplifier.

When the soft-start capacitor is around 1V, the
voltage at the positive input of the erro r amplifier
is approximately 0.6V.

The output of error amplifier will start increasing
and generating the first PWM signal. As the soft­start capacitor voltage continues to rise up, the
current flowing into the Fb pin will keep
decreasing.

The feedback voltage increases linearly as the
soft start voltage ramps up. When soft-start
voltage is around 2V, the output voltage r eaches
the steady state and the injected current is zero.

Figure 6 shows the theoretical operating
waveforms during soft-start.

The output voltage start-up time is the time
period when soft-start capacitor voltage
increases from 1V to 2V.

The start-up time will be dependent on the size of
the external soft-start capacitor and can be
estimated by:

Fig. 5: Soft-Start circuit for IR3821

Fig. 6: Theoretical operation waveforms

during soft-start

20uA

40uA

POR

Error Am p

SS/SD

Fb

Comp

24K

0.6V

24K

3V

Soft-Sta rt

Voltage

Voltage at negative input

of Error Amp

Voltage at Fb pin

Current flowing

into Fb p in

40uA

0uA

0V

0.6V

≅

0.96V

0.6V

0V

3V

≅

2V

≅

1V

Output of UVLO

POR

For a given start-up time, the soft-start capacitor
can be estimated as:

V1V2

C

T

μA20

ss

start

−=∗

)1 --(msTA20C

startSS

)(*

μ

≅

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PD-60331

IR3821MPbF

Over-Current Protection

The over-current protection is performed by
sensing current through the R

DS(on)

of the low
side MOSFET. This method enhances the
converter’s efficiency and reduces cost by
eliminating a current sense resistor. As shown in
figure 7, an external resistor (R

SET

) is connected
between OCSet pin and the inductor point which
sets the current limit set point.

The internal current source develops a voltage
across R

SET

. When the low side MOSFET is
turned on, the inductor current flows through the
Q2 and results a voltage which is given by:

Fig. 7: Connection of over current sensing resistor

Fig. 8: 3uA current source for discharging

soft-start capacitor during hiccup

An over-current is detected if the OCSet pin goes
below ground. This trips the OCP comparator
and cycles the soft start function in hiccup mode.

The hiccup is performed by charging and
discharging the soft-start capacitor in a certain
slope rate. As shown in figure 8 a 3uA current
source is used to discharge the soft-start
capacitor.

The OCP comparator resets after every soft start
cycle. The converter stays in this mode until the
overload or short circuit is removed. The
converter will automatically recover.

)) --(I(R)R(IV

LDS(on)OCSetOCSetOCSet

2∗−∗=

0)I(R)R(IV

LDS(on)OCSetOCSetOCSet

=∗

−

∗=

)3 --(

R

IR

II

onDS

OCSetOCSet

criticalLSET

)(

)(

∗

==

Fig. 9: OCset pin during normal condition

Ch1: Inductor point, Ch3:OCSet

The value of R

SET

should be checked in an actual
circuit to ensure that the over-current protection
circuit activates as e xpected. The IR3821 current
limit is designed primarily as disaster preventing,
and doesn't operate as a precision current
regulator.

The critical inductor current can be ca lculated by
setting:

I

OCSet*ROCSet

Blanking time

Deadtime

Clamp voltage

The OCP circuit starts sampling cu rrent when the
low gate drive is about 3V. The OCSet pin is
internally clamped about 1.5V during on time of
high side gate to prevent false trigging, figure 9
shows the OCSet pin during one sw itching cyc le.
As shown, there is about 150ns delay to mask
the dead time. Since this node contains switching
noises, this delay also functions as a filter.

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PD-60331

IR3821MPbF

Application Information

Design Example:

The following example is a typical application for
the IR3821. The application circuit is shown in
page 17.

Output Voltage Programming

Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier , which
is internally referenced to 0.6V. The divider is
ratioed to provide 0.6V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:

When an external resistor divider is connected to
the output as shown in figure 10.

Equation (4) can be rewritten as:

For the calculated values of R

8

and R9see

feedback compensation section.

kHz600F

mV30ΔV

A7I

V8.1V

)maxV,2.13V,(12V

s

o

o

o

in

=

=

=

=

≤

)4 --(

R

R

1VV

9

8

refo

⎟

⎟
⎠

⎞

⎜

⎜
⎝

⎛

+∗=

Fig. 10: Typical application of the IR3821 for

programming the output voltage

)5 --(

VV

V

RR

refO

ref

89

⎟

⎟
⎠

⎞

⎜

⎜
⎝

⎛

−

∗=

Soft-Start Programming

The soft-start timing can be programmed by
selecting the soft-start capacitance value. The
start-up time of the converter can be calculated
by using:

Where T

start

is the desired start-up time (ms)
For a start-up time of 11ms, the soft-start
capacitor will be 0.22uF.

Vc supply for single input voltage

To drive the high-side switch, it is necessary to
supply a gate voltage at least 4V greater than the
bus voltage. This is achieved by using a charge
pump configuration as shown in figure 11. This
method is simple and inexpensive. The operation
of the circuit is as follows: when the lower
MOSFET is turned on, the capacitor (C1) is
pulled down to ground and charges, up to V

BUS

value, through the diode (D1). The bus voltage
will be added to this voltage when upper
MOSFET turns on in next cycle, and providing
supply voltage (Vc) through diode (D2). Vc is
approximately:

Capacitors in the range of 0.1uF are generally
adequate for most applications. The diodes must
be a fast recovery device to minimize the amount
of charge fed back from the charge pump
capacitor into V

BUS

. The diodes need to be able
to block the full power rail voltage, which is seen
when the high-side MOSFET is switched on. For
low-voltage application, schottky diodes can be
used to minimize forward d rop across the diodes
at start up.

Fig. 11: Charge pump circuit to generate

Vc voltage

(

)

)6 --(VVV2V

2D1DbusC

+−∗

≅

)1 --(TA20C

startSS

*

μ

≅

Fb

IR3624

V

OUT

R

9

R

8

IR3821

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PD-60331

IR3821MPbF

Input Capacitor Selection

The input filter capacitor should be selected
based on how much ripple the supply can
tolerate on the DC input line. The ripple current
generated during the on time of upper MOSFET
should be provided by the input capacitor. The
RMS value of this ripple is expressed by:

Where:
D is the Duty Cycle
I

RMS

is the RMS value of the input capacitor

current.
Io is the output current.
For Io=7A and D=0.15, the I

RMS

=2.5A.

Ceramic capacitors are recommended due to
their peak current capabilities. They also feature
low ESR and ESL at higher frequency which
enables better efficiency.

Use 3x10uF, 16V ceramic capacitors from
Panasonic.

Inductor Selection

The inductor is selected based on output power ,
operating frequency and efficiency require ments.
A low inductor value causes a large ripple
current, resulting in the smaller size, faster
response to a load transient but poor efficiency
and high output noise. Generally, the selection of
the inductor value can be reduced to the desired
maximum ripple current in the inductor . The
optimum point is usually found between 20% and
50% ripple of the output current.

For the buck converter , the inducto r value for the
desired operating ripple current can be
determined using the following:

Where:

)7 --(D1DII

oRMS

)( −∗∗=

in

o

V

V

D =

s

oin

F

1

Dt

t

i

LVV ∗=∗=−

Δ

Δ

Δ

;

)( i

Δ

()

)8 --(

FiV

V

VVL

sin

o

oin

*

Δ

∗

∗−=

cycle DutyD

time on Turnt

frequency SwitchingF

current ripple Inductori

Voltage OutputV

voltage input MaximumV

s

o

in

=

=

=

=

=

=

Δ

Δ

If , then the output inductor will be:
L = 1.0uH
Delta MLP-105 series provides a range of

inductors in different values and low profile
suitable for large currents.

Output Capacitor Selection

The voltage ripple and transient requirements
determine the output capacitors’ type and values.
The criteria is normally based on the value of the
Effective Series Resistance ( ESR). However the
actual capacitance value and the Equivalent
Series Inductance (ESL) are other contributing
components. These components can be
described as:

Since the output capacitor has a major role in the
overall performance of the converter and
determine the result of transient response,
selection of the capacitor is critical. The IR3821
can perform well with all types of capacitors.

As a rule the capacitor must have low enough
ESR to meet output ripple and load transient
requirements, yet have high enough ESR to
satisfy stability requirements.

The goal for this design is to meet the voltage
ripple requirement in the smallest possible
capacitor size. Therefore, a ceramic capac itor is
selected due to its low ESR and small size. Six of
the Panasonic ECJ2FB0J226M (22uF, 6.3V, X5R
and EIA 0805 case size) are a good choice.

In the case of tantalum or low ESR electrolytic
capacitors, the ESR dominates the output
voltage ripple, equation (9) can be used to
calculate the required ESR for the specific
voltage ripple.

)%(40oIi

≈

Δ

current ripple InductorI

ripple voltage OutputV

FC8

I

V

ESL

L

V

V

-(9)- ESRIV

VVVV

L

o

so

L

Co

in

ESLo

LESRo

CoESLoESRoo

=

=

=

⎟
⎠

⎞

⎜
⎝

⎛

=

=

++=

Δ

Δ

Δ

Δ

Δ

ΔΔ

ΔΔΔ

Δ

**

*

*

)(

)(

)(

)()()(

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PD-60331

IR3821MPbF

Feedback Compensation

The IR3821 is a voltage mode controller; the
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed loop transfer
function with the highest 0dB crossing fr equency
and adequate phase margin (greater than 45

o

).

The output LC filter introduces a double pole, –
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180

o

(see figure 13). The resonant frequency of the LC
filter expressed as follows:

Figure 13 shows gain and phase of the LC filter.
Since we already have 180

o

phase shift from the
output filter alone, the system risks being
unstable.

The IR3821’s error amplifier is a di fferential-input
transconductance amplifier. The output is
available for DC gain control or AC phase
compensation.

The error amplifier can be compensated either in
type II or type III compensation. When it is used
in type II compensation the transconductance
properties of the error amp lifier become evident
and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC
circuit from Comp pin to ground as shown in
figure 14.

This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.

(11)---

CLπ2

1

F

oo

LC

=

Gain

F

LC

0dB

Phase

0



F

LC

-180



Frequency

Frequency

-40dB/decade

Fig. 13: Gain and Phase of LC filter

The ESR zero of the output capacitor expressed
as follows:

The transfer function (Ve/Vo) is given by:

The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:

The gain is determined by the voltage divider and
error amplifier’s transconductance gain.
First select the desired zero-c rossover fr equency
(Fo):

Use the following equation to calculate R3:

Where:
V

in

= Maximum Input Voltage

V

osc

= Oscillator Ramp Voltage

F

o

= Crossover Frequency

F

ESR

= Zero Frequency of the Output Capacitor

F

LC

= Resonant Frequency of the Output Filter

R

8

and R9= Feedback Resistor Dividers

g

m

= Error Amplifier Transconductance

(12)---

CESR2

1

F

o

ESR

**

π

∗

=

Fig. 14: TypeII compensation network

and its asymptotic gain plot

(13)---

sC

CsR1

*

RR

R

*g)s(H

4

43

89

9

m

+

+

=

()

[]

(15)---

CR2

1

F

(14)--- R*

RR

R

gsH

43

z

3

89

9

m

**

*

π

=

⎟

⎟
⎠

⎞

⎜

⎜
⎝

⎛

+

=

(

)

soESRo

F1/10~1/5F and FF *

≤

>

(16)---

g*R*F*V

)RR(*F*F*V

R

m9

2

LCin

98ESRoosc

3

+

=

Ve

V

OUT

V

REF

R

9

R

8

R

3

C

4

E/A

F

Z

H(s) dB

Frequency

Gain(dB)

Fb

Comp

C

POLE

01/08/08

14

PD-60331

IR3821MPbF

To cancel one of the LC filter poles, place the
zero before the LC filter resonant frequency pole:

Use equations (15) and (16) to calculate C4.
One more capacitor is sometimes added in
parallel with C4 and R3. This introduces one
more pole which is mainly used to suppress the
switching noise.
The additional pole is given by:

The pole sets to one half of switching fr equency
which results in the capacitor C

POLE

:

For a general solution for unconditional stability
for any type of output capacitors, in a wide range
of ESR values we should implement local
feedback with a compensation network (type III).
The typically used compensation network for
voltage-mode controller is shown in figure 15.

In such a configuration, the transfer function is
given by:

The error amplifier gain is independent of the
transconductance under the following condition:

By replacing Z

in

and Zf according to figure 15, the

transformer function can be expressed as:

(17)---

CL2

1

750F

F75F

oo

z

LCz

*

*.

%

π

=

=

As known, the transconductance amplifier has
high impedance (current source) output,
therefore, consideration should be taken when
loading the error amplifie r output. It may exceed
its source/sink output current capability, so that
the amplifier will not be able to swing its output
voltage over the necessary range.

The compensation network has three poles and
two zeros and they are expressed as follows:

Cross over frequency is expressed as:

CC

CC

R2

1

F

POLE4

POLE4

3

P

+

=

*

**

π

2

F

F For

FR*

1

C

1

FR

1

C

s

P

s3

4

s3

POLE

<<

≅

−

=

*

**

π

π

Fig.15: Compensation network with local

feedback and its asymptotic gain plot

INm

fm

o

e

Zg1

Zg1

V

V

+

−

=

(

)

[]

)(*

*

*)(

*

)(

)(

710

34

34

3

108743

348

CsR1

CC

CC

sR1

RRsC1CsR1

CCsR

1

sH

+

⎥
⎦

⎤
⎢
⎣

⎡

⎟

⎟
⎠

⎞

⎜

⎜
⎝

⎛

+

+

+

++

+

=

871087

2z

43

1z

33

34

34

3

3P

710

2P

1P

RC2

1

RRC2

1

F

CR2

1

F

CR2

1

CC

CC

R2

1

F

CR2

1

F

0F

**)(**

**

**

*

*

**

ππ

π

π

π

π

≅

+

=

=

≅

⎟

⎟
⎠

⎞

⎜

⎜
⎝

⎛

+

=

=

=

ooosc

in

73o

CL2

1

V

V

CRF

**

***

π

=

(18)--- 1Z*g and 1Z*g

inmfm

>>>>

V

OUT

V

REF

R

9

R

8

R

10

C

7

C

3

C

4

R

3

Ve

F

Z

1

F

Z

2

F

P

2

F

P

3

E/A

Z

f

Z

IN

Frequency

Gain(dB)

H(s) dB

Fb

Comp

01/08/08

15

PD-60331

IR3821MPbF

Based on the frequency of the zero generated by
the output capacitor and its ESR versus
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of crossover
frequency.

The DC gain will be large enough to provide high
DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greate r than 45

o

for

overall stability.
Desired Phase Boost:

Ceramic

FLC<Fo<F

s/2<FESR

Type III(PID)

Method B

Tantalum,

ceramic

FLC<Fo<F

ESR<Fs/2

Type III(PID)

Method A

Electrolytic
, Tantalum

FLC<F

ESR<Fo<Fs/2

Typ II(PI)

Output
capacitor

F

ESR

vs. F

o

Compensator
type

ΩK1.30R :Select ,ΩK20.30R ;R*

VV

V

R

ΩK4.60R:Select ,ΩK72.60R ;R

F*C*π2

1

R

ΩK96.1R :Select

g

1

R check ,ΩK95.1R ;

F*C*π2

1

R

:R and R ,R Calculate

pF22C :

Select ,pF26.25C ;

R*F*π2

1

C

nF0.1C :Select 1.07nF,C ;

R*F*π2

1

C

:C and C Calculate

Ω21KR :Select

g

2

R check ,KΩ94.20=R ,

V*C

V*C*L*F*π2

R

180pFC :Select

F*0.5F and F*5.0

F :Select

kHz7.453F

ΘSin1

ΘSin1

*FF

kHz1.14F

ΘSin1

ΘSin1

*FF

998

refo

ref

9

8810

2Z7

8

10

m

1010

2P7

10

9810

33

33P

3

44

3

Z1

4

34

3

m

33

in7

OSCooo

3

7

sP32ZZ1

2P

o2P

2Z

o2Z

===

===

=

==

===

===

=

=

=

==

=

+

=

=

+

=

≥

≥

-

-

o

max

70Θ =

Table1- The compensation type and location

of F

ESR

versus F

o

The details of these compensation types are
discussed in application note AN-1043 wh ich can
be downloaded from IR’s website at www.irf.com.

For this design we have:
V

in

=12V

V

o

=1.8V

V

osc

=1.25V

V

ref

=0.6V

g

m

=1000umoh

L

o

=1.0uH

C

o

=6x22uF, ESR=0.8mOhm

F

s

=600kHz

These result to:

FLC=18.76kHz
F

ESR

=4.4MHz

F

s/2

=300kHz

Select crossover frequency:

Fo=80kHz

Since: F

LC<Fo<Fs/2<FESR

, typeIII method B is

selected to place the poles and zeros.
The following design rules will give a crossover

frequency approximately one-tenth of the
switching frequency. The higher the band width,
the potentially faster the load transient response.

(

)

soESRo

F1/10~1/5F and FF *≤<

01/08/08

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PD-60331

IR3821MPbF

Programming the Current-Limit

The Current-Limit threshold can be set by
connecting a resistor (R

SET

) from drain of the
low-side MOSFET to the OCSet pin. The
resistor can be calculated by using equation (3).
The R

DS(on)

has a positive temperature
coefficient and it should be considered for the
worse case operation. This resistor must be
placed close to the IC, place a small ceramic
capacitor from this pin to powe r ground (PGnd)
for noise rejection purposes.

-(3)-

R

IR

=I=I

DS(on)

OCSetOCSet

)L(criticalSET

-

Layout Consideration

The layout is very important w hen designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
Start to place the power components, making all
the connection in the top layer with wide, copper
filled areas.
The inductor, output capacitor and the IR3821
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly to
the Vin pin of IR3821. To reduce the ESR replace
the single input capacitor with two parallel units.
The feedback part of the system should be kept
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vcc and Vc should be close to their
respective pins. It is important to place the
feedback components including feedback
resistors and compensation components close to
Fb and Comp pins.
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
current path to a separate loop that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4-layers PC B. To
effectively remove heat from the device the
exposed pad should be connected to the gr ound
plane using vias.

Setting the Power Good Threshold

Power Good threshold can be programmed by
using two external resistors (see figure 16).

The following formula can be used to set the
threshold:

Where:

0.38V is reference of the internal comparator

0.9*Vout is selectable threshold for power good,
for this design it is 1.62V.

Select R

1

=10KOhm

Using (18): R

2

=3.06KOhm

Select R

2

=3.09K
Use a pull up resistor (4.99K) from PGood pin to
Vcc.

)19 --(*R

V38.0*V9.0

V38.0

R

1

out

2

-

=

8.45KΩ=R=R

11.7A=1.2A1.5)*(7A=II

F*L*V

V

*)VV(iΔ

current inductor Peak:iΔ

Current Output Max:I

:where

2

iΔ

)5.1*(I=II

V for usedis 5V if

MOSFET side-low for mΩ 14.5 Use :Note

14.25mΩ=.51* 9.5mΩ=R

7OCSet

o(LIM)SET

sin

o

oin

o

oo(LIM)SET

cc

DS(on)

+=

=+=-

01/08/08

17

PD-60331

IR3821MPbF

Typical Application for IR3821

12V to 1.8V @ 7A

Fig.16: Typical Application circuit for 12V to 1.8V at 7A using ceramic output capacitors

01/08/08

18

PD-60331

IR3821MPbF

PCB Metal and Components Placement

The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The
minimum lead-to-lead spacing should be ≥ 0.2mm to minimize shorting.

Lead land length should be equal to the maximum part lead length + 0.3 mm outboard
extension. The outboard extension ensures a large and inspectable toe fillet.

The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal
to maximum part pad length and width. However, the minimum metal-to-metal spacing
should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper
and no less than 0.23mm for 3 oz. Copper.

01/08/08

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PD-60331

IR3821MPbF

Solder Resist

It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder
resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure
NSMD pads.

The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder
resist onto the copper of 0.05mm to accommodate solder resist misalignment.

Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to
the high aspect ratio of the solder resist strip separating the lead lands from the pad land.

01/08/08

20

PD-60331

IR3821MPbF

Stencil Design

• The Stencil apertures for the lead lands should be approximately 80% of the area of
the lead lads. Reducing the amount of solder deposited will minimize the
occurrences of lead shorts. If too much solder is deposited on the center pad the part
will float and the lead lands will be open.

• The maximum length and width of the land pad stencil aperture should be equal to
the solder resist opening minus an annular 0.2mm pull back to decrease the
incidence of shorting the center land to the lead lands when the part is pushed into
the solder paste.

01/08/08

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PD-60331

IR3821MPbF

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

TAC Fax: [phone]

This product has been designed and qualified for the Consumer mark et.

Visit us at www.irf.com for sales contact information

Data and specifications subject to change without notice. 10/07