Datasheet IR 2184 Datasheet

Data Sheet No. PD60174 Rev.D

IR2184(4

)(S)

HALF-BRIDGE DRIVER

Features

Floating channel designed for bootstrap operation

•

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune

Gate drive supply range from 10 to 20V

•

Undervoltage lockout for both channels

•

3.3V and 5V input logic compatible

•

Matched propagation delay for both channels

•

Logic and power ground +/- 5V offset.

•

Lower di/dt gate driver for better noise immunity

•

Output source/sink current capability 1.4A/1.8A

•

Description

The IR2184(4)(S) are high voltage,
high speed power MOSFET and IGBT
drivers with dependent high and low
side referenced output channels. Pro­prietary HVIC and latch immune
CMOS technologies enable rugge­dized monolithic construction. The
logic input is compatible with standard
CMOS or LSTTL output, down to 3.3V
logic. The output drivers feature a high
pulse current buffer stage designed for
minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or
IGBT in the high side configuration which operates up to 600 volts.

IR2181/IR2183/IR2184 Feature Comparison

Part

2181 COM

21814

2183 Internal 500ns COM

21834

2184 Internal 500ns COM

21844

Packages

14-Lead PDIP

8-Lead SOIC

IR2184S

8-Lead PDIP

IR2184

Input
logic

HIN/LIN no none

HIN/LIN yes

IN/SD yes

Cross­conduction
prevention

logic

Dead-Time Ground Pins Ton/Toff

Program 0.4 ~ 5 us VSS/COM

Program 0.4 ~ 5 us VSS/COM

IR21844

VSS/COM

14-Lead SOIC

IR21844S

180/220 ns

180/220 ns

680/270 ns

Typical Connection

up to 600V

V

CC

V

V

IN

SD

(Refer to Lead Assignments for correct
configuration). This/These diagram(s) show
electrical connections only. Please refer to
our Application Notes and DesignTips for
proper circuit board layout.

CC

IN
SD

www.irf.com 1

B

HO

V

S

LOCOM

IR2184

TO

LOAD

up to 600V

HO

V

V

CC

IN

SD

V

SS

R

DT

V

CC

IN
SD
DT
V

B

V

S

COM

SS

LO

IR21844

TO

LOAD

IR2184(4)

(S)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

DT Programmable dead-time pin voltage (IR21844 only) VSS - 0.3 V

V

IN

V

SS

dVS/dt Allowable offset supply voltage transient — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High side floating absolute voltage -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V

B

+ 0.3
Low side and logic fixed supply voltage -0.3 25
Low side output voltage -0.3 VCC + 0.3

+ 0.3

CC

Logic input voltage (IN & SD) VSS - 0.3 V
Logic ground (IR21844 only) V

- 25 V

CC

SS

CC

+ 10

+ 0.3

Package power dissipation @ TA ≤ +25°C (8-lead PDIP) — 1.0

(8-lead SOIC) — 0.625
(14-lead PDIP) — 1.6
(14-lead SOIC) — 1.0

Thermal resistance, junction to ambient (8-lead PDIP) — 125

(8-lead SOIC) — 200

(14-lead PDIP) — 75

(14-lead SOIC) — 120
Junction temperature — 150
Storage temperature -50 150
Lead temperature (soldering, 10 seconds) — 300

V

W

°C/W

°C

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential.

Symbol Definition Min. Max. Units

VB High side floating supply absolute voltage VS + 10 VS + 20

V

S

V

HO

V

CC

V

LO

V

IN

DT Programmable dead-time pin voltage (IR21844 only) V

V

SS

T

A

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: IN and SD are internally clamped with a 5.2V zener diode.

High side floating supply offset voltage Note 1 600
High side floating output voltage V

S

V

B

Low side and logic fixed supply voltage 10 20
Low side output voltage 0 V
Logic input voltage (IN & SD) V

SS
SS

CC

V

+ 5

SS

V

CC

Logic ground (IR21844 only) -5 5
Ambient temperature -40 125 °C

V

2 www.irf.com

IR2184(4)

(S)

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15V, VSS = COM, CL = 1000 pF, TA = 25°C, DT = VSS unless otherwise specified.

BIAS

Symbol Definition Min. Typ. Max. Units Test Conditions

t

on

t

off

t

sd Shut-down propagation delay

MTon Delay matching, HS & LS turn-on — 0 90

MToff Delay matching, HS & LS turn-off — 0 40

t
t

DT Deadtime: LO turn-off to HO turn-on(DT

MDT Deadtime matching = DT

Turn-on propagation delay — 680 900 VS = 0V
Turn-off propagation delay — 270 400 VS = 0V or 600V

— 180 270

nsec

Turn-on rise time — 40 60 VS = 0V

r

Turn-off fall time — 20 35 VS = 0V

f

280 400 520 RDT= 0
456µsec RDT = 200k
— 0 50 RDT=0

— 0 600 RDT = 200k

nsec

HO turn-off to LO turn-on (DT

LO - HO

- DT

HO-LO

LO-HO) &

HO-LO)

Static Electrical Characteristics

V

(VCC, VBS) = 15V, VSS = COM, DT= VSS and TA = 25°C unless otherwise specified. The VIL, VIH and I

BIAS

parameters are referenced to V
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.

/COM and are applicable to the respective input leads: IN and SD. The VO, IO and Ron

SS

Symbol Definition Min. Typ. Max. Units Test Conditions

V

IH

V

V

SD,TH+ SD input positive going threshold 2.7

V

SD,TH- SD input negative going threshold

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

V

CCUV+VCC

V

BSUV+

V

CCUV-

V

BSUV-

V

CCUVH

V

BSUVH

I

O+

I

O-

Logic “1” input voltage for HO & logic “0” for LO 2.7 — — VCC = 10V to 20V
Logic “0” input voltage for HO & logic “1” for LO — — 0.8 VCC = 10V to 20V

IL

—— VCC = 10V to 20V

——
High level output voltage, V
Low level output voltage, V
Offset supply leakage current — — 50 VB = VS = 600V
Quiescent VBS supply current 20 60 150 V
Quiescent VCC supply current 0.4 1.0 1.6 mA VIN = 0V or 5V
Logic “1” input bias current — 5 20 IN = 5V, SD = 0V
Logic “0” input bias current — 1 2 IN = 0V, SD = 5V

and VBS supply undervoltage positive going 8.0 8.9 9.8
threshold
VCC and V
threshold

Hysteresis 0.3 0.7 —

Output high short circuit pulsed current 1.4 1.9 — VO = 0V,

Output low short circuit pulsed current 1.8 2.3 — VO = 15V,

supply undervoltage negative going 7.4 8.2 9.0

BS

BIAS

O

- V

O

— — 1.2 IO = 0A
— — 0.1 IO = 0A

0.8

V

µA

µA

V

A

IN

VCC = 10V to 20V

= 0V or 5V

IN

PW ≤ 10 µs

PW ≤ 10 µs

www.irf.com 3

IR2184(4)

(S)

Functional Block Diagrams

2184

IN

VSS/COM

LEVEL

SHIFT

PULSE

GENERATOR

HV

LEVEL

SHIFTER

PULSE
FILTER

UV

DETECT

VB

R

Q

R

S

HO

VS

SD

DT

VCC

LO

COM

+5V

DEADTIME

VSS/COM

LEVEL

SHIFT

DELAY

UV

DETECT

VB

UV

PULSE
FILTER

DETECT

DETECT

R

Q

R

S

HO

VS

VCC

UV

LO

21844

HV

LEVEL

IN

DEADTIME

+5V

VSS/COM

LEVEL
SHIFT

PULSE

GENERATOR

SHIFTER

SD

LEVEL
SHIFT

DELAY

COM

VSS/COM

VSS

4 www.irf.com

IR2184(4)

Lead Definitions

Symbol Description

IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM

for IR2184 and VSS for IR21844)

SD

Logic input for shutdown (referenced to
DT Programmable dead-time lead, referenced to VSS. (IR21844 only)
VSS Logic Ground (21844 only)
V

B

High side floating supply
HO High side gate drive output
V

S

V

CC

High side floating supply return

Low side and logic fixed supply
LO Low side gate drive output
COM Low side return

Lead Assignments

COM for IR2184 and VSS for IR21844)

(S)

1

IN

2

SD

3

COM

4

LO

V

8

B

HO

7

V

6

S

V

5

CC

1

IN

2

SD

3

COM

4

LO

8-Lead PDIP 8-Lead SOIC

IR2184 IR2184S

V

HO

V

14

13

B

12
11

S

10

9
8

1

IN

2

SD

3

VSS

4

DT

5

COM

6

LO

7

V

CC

14-Lead PDIP 14-Lead SOIC

1

IN

2

SD

3

VSS

4

DT

5

COM

6

LO

7

V

CC

IR21844 IR21844S

V

8

B

HO

7

V

6

S

V

5

CC

14

V

13

B

HO

12

V

11

S

10

9
8

www.irf.com 5

IR2184(4)

(S)

A

E

D B

5

87

6

6X

0.25 [.010]

65

H

4312

0.25 [.010] A

e

8X b

e1

A1

A

CAB

NOTES:

1. DIMENS IONING & TOLE RAN CING PE R ASME Y14.5M-199 4.

2. CONTROLLING DIMENSION: MILLIMETER

3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].

4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.

C

0.10 [.004]

8-Lead PDIP

6.46 [.255]

3X 1.27 [.050]

y

8-Lead SOIC

01-3003 01

DIM

FOOTPRINT

8X 0.72 [.028]

8X 1.78 [.070]

MIN MAX

.0532

A

A1

b

c .0075 .0098 0.19 0.25

D

E

e

e1

H

K

L

y

.0688

.0040

.0098

.020

.013

.1968

.189

.1574

.1497

.050 BAS IC

.025 BA SIC 0.635 BAS IC

.2284

.2440

.0099

.0196

.016

.050

0°

K x 45°

8X L

8X c

7

5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOL D PR OTR US ION S N OT TO EX C EE D 0.15 [.006].

6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOL D PR OTR US ION S N OT TO EX C EE D 0.25 [.010].

7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SU BSTRA TE.

01-0021 11

8°

01-6014

(MS-001AB)

MILLIMETERSIN C H E S

MIN MAX

1.35

1.75

0.10

0.25

0.33

0.51

4.80

5.00

3.80

4.00

1.27 BAS IC

5.80

6.20

0.25

0.50

0.40

1.27

0°

8°

01-6027

(MS-012AA)

6 www.irf.com

14-Lead PDIP

IR2184(4)

01-6010

01-3002 03

(MS-001AC)

(S)

14-Lead SOIC (narrow body)

www.irf.com 7

01-3063 00

01-6019

(MS-012AB)

IR2184(4)

(S)

IN

SD

HO

LO

IN

IN

LO
HO

(LO)

(HO)

t

on

50%

t

r

50%

t

off

90% 90%

10% 10%

Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions

SD

HO

50%

t

sd

IN

90%

50% 50%

90%

LO

Figure 3. Shutdown Waveform Definitions

IN

(LO)

LO

50%

HO

50%

IN

(HO)

HO

LO

DT

Figure 4. Deadtime Waveform Definitions

LO-HO

MDT=

90%

DT

10%

LO-HO

- DT

DT

HO-LO

HO-LO

10%

t

f

10%

MT

90%

MT

HOLO

Figure 5. Delay Matching Waveform Definitions

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: [phone]

Data and specifications subject to change without notice. 7/24/2001

8 www.irf.com

This datasheet has been download from:

www.datasheetcatalog.com

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