Datasheet IR2152 Datasheet (IOR)

Preliminary Data Sheet No. PD60035J

recommend IR’s new products IR2154 and IR21541)

SELF-OSCILLATING HALF-BRIDGE DRIVER

Features

Floating channel designed for bootstrap operation

•

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Undervoltage lockout

•

Programmable oscillator frequency

•

f =

1.4 (R 75 ) C

Matched propagation delay for both channels

•

Low side output in phase with R

•

Description

The IR2152 is a high voltage, high speed, self­oscillating power MOSFET and IGBT driver with both
high and low side referenced output channels. Pro­prietary HVIC and latch immune CMOS technologies
enable ruggedized monolithic construction. The front
end features a programmable oscillator which is simi­lar to the 555 timer. The output drivers feature a high
pulse current buffer stage and an internal deadtime
designed for minimum driver cross-conduction. Propa­gation delays for the two channels are matched to sim­plify use in 50% duty cycle applications. The floating
channel can be used to drive an N-channel power
MOSFET or IGBT in the high side configuration that
operates off a high voltage rail up to 600 volts.

1

×+ ×

Ω

TT

T

IR2152

(NOTE: For new designs, we

Product Summary

V

OFFSET

Duty Cycle 50%

IO+/ - 100 mA / 210 mA

V

OUT

Deadtime (typ.) 1.2 µs

Packages

8 Lead PDIP

600V max.

10 - 20V

8 Lead SOIC

T ypical Connection

(Refer to Lead Assignment diagram for correct pin configuration)

up to 600V

V

CC

R

T

C

T

V

HO

V

LOCOM

B

S

TO

LOAD

1

IR2152

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

LO

V

RT

V

CT

I

CC

I

RT

dVs/dt Allowable offset supply voltage transient — 50 V/ns

P

D

R

THJA

T

J

T

S

T

L

High side floating supply voltage -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V

B

+ 0.3
Low side output voltage -0.3 VCC + 0.3
RT voltage -0.3 VCC + 0.3
CT voltage -0.3 V
Supply current (note 1) — 25
RT output vurrent -5 5

CC

+ 0.3

mA

Package power dissipation @ TA ≤ +25°C (8 Lead DIP) — 1.0

(8 Lead SOIC) — 0.625

Thermal resistance, junction to ambient (8 Lead DIP) — 125

(8 Lead SOIC) — 200

°C/W

Junction temperature — 150
Storage temperature -55 150 °C
Lead temperature (soldering, 10 seconds) — 300

V

W

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

LO

I

CC

T

A

Note 1: Because of the IR2152’s application specificity toward off-line supply systems, this IC contains a zener clamp

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High Side Floating Supply Absolute Voltage VS + 10 VS + 20
High Side Floating Supply Offset Voltage — 600
High Side Floating Output Voltage V

S

Low Side Output Voltage 0 V

V

CC

B

V

Supply Current (Note 1) — 5 mA
Ambient Temperature -40 125 °C

structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Therefore, the IC
supply voltage is normally derived by forcing current into the supply lead (typically by means of a high value
resistor connected between the chip VCC and the rectified line voltage and a local decoupling capacitor from
VCC to COM) and allowing the internal zener clamp circuit to determine the nominal supply voltage. There­fore, this circuit should not be driven by a DC, low impedance power source of greater than V

CLAMP

.

IR2152

Dynamic Electrical Characteristics

V

(VCC, VBS) = 12V, CL = 1000 pF and TA = 25°C unless otherwise specified.

BIAS

Symbol Definition Min. Typ. Max. Units Test Conditions

t
t

DT Deadtime 0.50 1.20 2.25 µs

DR

Static Electrical Characteristics

V

(VCC, VBS) = 12V, CL = 1000 pF, CT = 1 nF and TA = 25°C unless otherwise specified. The VIN, VTH and I

BIAS

parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the
respective output leads: HO or LO.

Symbol Definition Min. Typ. Max. Units T est Conditions

f

OSC

V

CLAMP

V

CT+

V

CT-

V

CTUV

V

RT+

V

RT-

V

RTUV

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

CT

V

CCUV+

V

CCUV-

V

CCUVH

I

O+

I

O-

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Turn-on rise time — 80 120

r

Turn-off fall time — 40 70

f

duty cycle 48 50 52 %

T

Oscillator frequency 19.4 20.0 20.6 RT = 35.7 kΩ

94 100 106 RT = 7.04 kΩ

ns

kHz

VCC zener shunt clamp voltage 14.4 15.6 16.8 ICC = 5 mA
2/3 VCC threshold 7.8 8.0 8.2 V
1/3 VCC threshold 3.8 4.0 4.2
CT undervoltage lockout, VCC - C

T

RT high level output voltage, VCC - R

T

— 20 50 2.5V<VCC<V
— 0 100 IRT = -100 µA
— 200 300 IRT = -1 mA

RT low level output voltage — 20 50 IRT = 100 µA

— 200 300 IRT = 1 mA

mV

RT undervoltage lockout — 0 100 2.5V<VCC<V
High level output voltage, V
Low level output voltage, V

BIAS

O

- V

O

— — 100 IO = 0A

— — 100 IO = 0A
Offset supply leakage current — — 50 VB = VS = 600V
Quiescent VBS supply current — 10 50
Quiescent VCC supply current — 400 950

µA

CT input current — 0.001 1.0
VCC supply undervoltage positive going 7.7 8.4 9.2

threshold
VCC supply undervoltage negative going 7.4 8.1 8.9

V

threshold
VCC supply undervoltage lockout hysteresis 200 500 — mV
Output high short circuit pulsed current 100 125 — VO = 0V
Output low short circuit pulsed current 210 250 — VO = 15V

mA

IN

CCUV+

CCUV+

IR2152

Functional Block Diagram

UV

DETECT

R

T

C

T

Lead Definitions

Symbol Description

R

T

C

T

V

B

HO High side gate drive output
V

S

V

CC

LO Low side gate drive output
COM Low side return

R

­RQ

+

R

R

SQ

-

+

Oscillator timing resistor input,in phase with HO for normal IC operation
Oscillator timing capacitor input, the oscillator frequency according to the following equation:

f =

×+ ×

1.4 (R 75 ) C

where 75Ω is the effective impedance of the RT output stage
High side floating supply

High side floating supply return
Low side and logic fixed supply

HV
LEVEL
SHIFT

TIME

PULSE

GEN

DEAD

TIME

DEAD

1

Ω

TT

PULSE
FILTER

DELAY

R

S

15.6V

V

B

Q

HO

V

S

V

CC

LO

COM

Lead Assignments

8 Lead PDIP 8 Lead SOIC

IR2152 IR2152S

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IR2152

8 Lead PDIP

01-3003 01

8 Lead SOIC

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01-0021 08

IR2152

V

CLAMP

(LO)

R

T

50%

(HO)

T

R

T

t

r

50%

90% 90%

V

HO

CC

V

+

CCUV

C

T

R

LO

LO

Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions

R

T

50%

50%

HO

90%

LO

10%

DT

HO

90%

10% 10%

t

f

10%

Figure 3. Deadtime Waveform Definitions

WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: [phone]

http://www.irf.com/ Data and specifications subject to change without notice. 3/29/2001

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