n Gate drive supply range from 12 to 18V
n Undervoltage lockout
n Current detection and limiting loop to limit driven
power transistor current
n Error lead indicates fault conditions and programs
shutdown time
n Output in phase with input
Description
The IR2121 is a high speed power MOSFET and
IGBT driver with over-current limiting protection circuitry . Latch imm une CMOS technology enables ruggedized monolithic construction. Logic inputs are
compatible with standard CMOS or LSTTL outputs.
The output driver features a high pulse current b uffer
stage designed for minimum cross-conduction. The
protection circuitry detects over-current in the driven
power transistor and limits the gate drive voltage.
Cycle-by-cycle shutdown is programmed by an external capacitor which directly controls the time interval between detection of the over-current limiting
condition and latched shutdown. The output can be
used to drive an N-channel power MOSFET or IGBT
in the low side configuration.
Product Summary
V
OFFSET
IO+/-1A / 2A
V
OUT
V
CSth
t
(typ.)150 & 150 ns
on/off
Package
5V max.
12 - 18V
230 mV
Typical Connection
V
CC
IN
V
CC
IN
ERR
COM
V
CC
OUT
CS
V
TO
LOAD
S
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-91
Page 2
IR2121
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Ther mal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
ParameterValue
SymbolDefinitionMin.Max.Units
V
R
V
V
V
V
ERR
V
P
T
T
T
CC
S
O
IN
CS
D
θJA
J
S
L
Fixed Supply Voltage-0.325
Gate Drive Return VoltageVCC - 25VCC + 0.3
Output VoltageVS - 0.3V
Logic Input Voltage-0.3V
Error Signal Voltage-0.3V
Current Sense VoltageVS - 0.3V
CC
CC
CC
CC
+ 0.3
+ 0.3
+ 0.3
+ 0.3
V
Package Power Dissipation @ TA ≤ +25°C—1.0W
Thermal Resistance, Junction to Ambient—125°C/W
Junction Temperature—150
Storage Temperature-55150°C
Lead Temperature (Soldering, 10 seconds)—300
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V
SymbolDefinitionMin.Max.Units
V
CC
V
S
V
O
V
IN
V
ERR
V
CS
T
A
B-92CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
Fixed Supply VoltageVS + 10VS + 20
Gate Drive Return Voltage-55
Output VoltageV
Logic Input Voltage0V
Error Signal Voltage0V
Current Sense Signal VoltageV
Ambient Temperature-40125°C
offset rating is tested with all supplies biased at 15V differential.
S
ParameterValue
S
S
V
CC
CC
CC
V
CC
V
Page 3
IR2121
Dynamic Electrical Characteristics
V
(VCC) = 15V, CL = 3300 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics are
BIAS
defined in Figures 2 through 5.
ParameterValue
SymbolDefinitionFigure Min.Typ. Max. Units Test Conditions
t
on
t
off
t
sd
t
t
t
cs
t
err
Static Electrical Characteristics
V
(VCC) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM.
BIAS
The V
O
SymbolDefinitionFigure Min.Typ. Max. Units Test Conditions
CS Input Positive Going Threshold16150230320VCC = 12V to 18V
CS Input Negative Going Threshold17130200260VCC = 12V to 18V
High Level Output Voltage, V
Low Level Output V oltage, V
ERR Pull-Down Current291630—
Output High Short Circuit Pulsed Current3 01.01.6—
Output Low Short Circuit Pulsed Current312.03.3—
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-93
V
mV
V
µA
V
µA
mA
A
ERR
V
=
IN
V
V
V
= 3V or 5V
CS
V
V
= 5V,
IN
ERR < V
V
= 5V,
IN
ERR > V
V
V
= 0V,
O
PW ≤ 10 µs
V
= 15V ,
O
PW ≤ 10 µs
= 270 pF
= 0V or 5V
CS
= 5V
IN
= 0V
IN
= 0V
CS
V
CS
ERR+
V
CS
ERR+
= 0V
IN
V
= 5V
IN
V
IN
= 3V
= 3V
= 0V
Page 4
IR2121
Functional Block Diagram
V
CC
UV
ERR
COM
DETECT
IN
1.8V
ERROR
TIMING
1.8V
PRE
DRIVER
500 ns
BLANK
BUFFER
0.23V
-
+
AMPLIFER
COMPARATOR
Lead Definitions
Lead
SymbolDescription
V
CC
INLogic input for gate driver output (OUT), in phase with OUT
ERRServes multiple functions; status reporting, linear mode timing and cycle by cycle logic
COMLogic ground
OUT
V
S
CS
Logic and gate drive supply
shutdown
Gate drive output
Gate drive supply return
Current sense input to current sense comparator
V
CC
OUT
V
S
CS
Lead Assignments
8 Lead DIP
IR2121
Part Number
B-94CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
Page 5
Device Information
Process & Design RuleHVDCMOS 4.0 µm
Transistor Count410
Die Size104 X 111 X 26 (mil)
Die Outline
Thickness of Gate Oxide800Å
ConnectionsMaterialPoly Silicon
FirstWidth4 µm
LayerSpacing6 µm
Thickness5000Å
MaterialAl - Si (Si: 1.0% ±0.1%)
SecondWidth6 µm
LayerSpacing9 µm
Thickness20,000Å
Contact Hole Dimension8 µm X 8 µm
Insulation LayerMaterialPSG (SiO2)
Thickness1.5 µm
PassivationMaterialPSG (SiO2)
(1)Thickness1.5 µm
PassivationMaterialProprietary*
(2)ThicknessProprietary*
Method of SawFull Cut
Method of Die BondAblebond 84 - 1
Wire BondMethodThermo Sonic
MaterialAu (1.0 mil / 1.3 mil)
LeadframeMaterialCu
Die AreaAg
Lead PlatingPb : Sn (37 : 63)
Pa ckageTypes8 Lead PDIP
MaterialsEME6300 / MP150 / MP190
Remarks:* Patent Pending
IR2121
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-95
Page 6
IR2121
IN
CS
OUT
ERR
OUT
IR2121
4
Figure 1. Input/Output Timing DiagramFigure 2. Switching Time T est Circuit