Datasheet IR2109 4-S Datasheet (IOR)

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Data Sheet No. PD60163-P

IR2109(4)

(S)

HALF-BRIDGE DRIVER

Features

Floating channel designed for bootstrap operation

•

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V

•

Undervoltage lockout for both channels

•

3.3V, 5V and 15V input logic compatible

•

Cross-conduction prevention logic

•

Matched propagation delay for both channels

•

High side output in phase with IN input

•

Logic and power ground +/- 5V offset.

•

Internal 540ns dead-time, and programmable

•

up to 5us with one external R
Lower di/dt gate driver for better noise immunity

•

Shut down input turns off both channels.

•

resistor (IR21094)

DT

Description

The IR2109(4)(S) are high voltage, high speed power
MOSFET and IGBT drivers with dependent high and
low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rugge­dized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output,
down to 3.3V logic. The output drivers feature a high
pulse current buffer stage designed for minim um driver
cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the
high side configuration which operates up to 600 volts.

Product Summary

V

OFFSET

I

+/- 120 mA / 250 mA

O

V

OUT

t

(typ.) 750 & 200 ns

on/off

Dead Time 540 ns

(programmable up to 5uS for IR21094)

600V max.

10 - 20V

Packages

14 Lead SOIC

8 Lead SOIC

14 Lead PDIP

8 Lead PDIP

Typical Connection

up to 600V

V

CC

V

V

CC

IN

SD

(Refer to Lead Assignments for correct
configuration). This/These diagram(s) show
electrical connections only. Please ref er to our
Application Notes and DesignTips for proper
circuit board layout.

IN
SD

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B

HO

V

S

LOCOM

IR2109

TO

LOAD

HO

V

V

CC

IN

SD

V

SS

R

DT

V

CC

IN
SD
DT
V

B

V

S

COM

SS

LO

IR21094

up to 600V

TO

LOAD

)

(

IR2109(4)

S

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

DT Programmable dead-time pin voltage (IR21094 only) VSS - 0.3 V

V

IN

V

SS

dVS/dt Allowable offset supply voltage transient — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High side floating absolute voltage -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V
Low side and logic fixed supply voltage -0.3 25
Low side output voltage -0.3 VCC + 0.3

Logic input voltage (IN & SD) VSS - 0.3 V
Logic ground (IR21094/IR21894 only) V

Package power dissipation @ TA ≤ +25°C (8 Lead PDIP) — 1.0

(8 Lead SOIC) — 0.625
(14 lead PDIP) — 1.6
(14 lead SOIC) — 1.0

Thermal resistance, junction to ambient (8 Lead PDIP) — 125

(8 Lead SOIC) — 200

(14 lead PDIP) — 75

(14 lead SOIC) — 120
Junction temperature — 150
Storage temperature -50 150
Lead temperature (soldering, 10 seconds) — 300

- 25 V

CC

CC
CC
CC

B

+ 0.3

+ 0.3
+ 0.3
+ 0.3

V

W

°C/W

°C

2 www.irf.com

IR2109(4)

(S)

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V

Symbol Definition Min. Max. Units

VB High side floating supply absolute voltage VS + 10 VS + 20

V

S

V

HO

V

CC

V

LO

V

IN

DT Programmable dead-time pin voltage (IR21094 only) V

V

SS

T

A

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).

High side floating supply offset voltage Note 1 600
High side floating output voltage V
Low side and logic fixed supply voltage 10 20
Low side output voltage 0 V
Logic input voltage (IN & SD) V

Logic ground (IR21094 only) -5 5
Ambient temperature -40 125 °C

and VSS offset rating are tested with all supplies biased at 15V differential.

S

S

SS
SS

V

B

CC

V

CC

V

CC

V

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15V, VSS = COM, CL = 1000 pF, TA = 25°C, DT = VSS unless otherwise specified.

BIAS

Symbol Definition Min. Typ. Max. Units Test Conditions

t

on

t

off

t

sd Shut-down propagation delay

MT Delay matching, HS & LS turn-on/off — 0 70

t
t

DT Deadtime: LO turn-off to HO turn-on(DT

MDT Deadtime matching = DT

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Turn-on propagation delay — 750 950 VS = 0V
Turn-off propagation delay — 200 280 VS = 0V or 600V

— 200 280

nsec

Turn-on rise time — 150 220 VS = 0V

r

Turn-off fall time — 50 80 VS = 0V

f

400 540 680 RDT= 0
4 5 6 usec RDT = 200k (IR21094)
— 0 60 RDT=0

— 0 600 RDT = 200k (IR21094)

nsec

HO turn-off to LO turn-on (DT

- DT

LO - HO

HO-LO

LO-HO) &

HO-LO)

)

(

IR2109(4)

S

Static Electrical Characteristics

V

(VCC, VBS) = 15V, VSS = COM, DT= VSS and TA = 25°C unless otherwise specified. The VIL, VIH and I

BIAS

parameters are referenced to V
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.

/COM and are applicable to the respective input leads: IN and SD. The VO, IO and Ron

SS

Symbol Definition Min. Typ. Max. Units Test Conditions

V

IH

V

V

SD,TH+ SD input positive going threshold 2.9

V

SD,TH- SD input negative going threshold

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

V

CCUV+VCC

V

BSUV+

V

CCUV-

V

BSUV-

V

CCUVH

V

BSUVH

I

O+

I

O-

Logic “1” input voltage for HO & logic “0” for LO 2.9 — — VCC = 10V to 20V
Logic “0” input voltage for HO & logic “1” for LO — — 0 .8 VCC = 10V to 20V

IL

—— V

——
High level output voltage, V
Low level output voltage, V
Offset supply leakage current — — 50 VB = VS = 600V
Quiescent VBS supply current 20 60 150 V
Quiescent VCC supply current 0.4 1.0 1 .6 mA VIN = 0V or 5V

Logic “1” input bias current — 5 20 IN = 5V, SD = 0V
Logic “0” input bias current — 1 2 IN = 0V, SD = 5V

and V
threshold
VCC and VBS supply undervoltage negative going 7. 4 8. 2 9.0
threshold
Hysteresis 0.3 0.7 —

Output high short circuit pulsed vurrent 120 200 — VO = 0V, PW ≤ 10 µs
Output low short circuit pulsed current 250 350 — VO = 15V,PW ≤ 10 µs

supply undervoltage positive going 8.0 8.9 9.8

BS

BIAS

O

- V

O

— 0.8 1.4 IO = 20 mA
— 0.3 0.6 IO = 20 mA

0.8

V

µA

µA

V

mA

IN

= 10V to 20V

CC

VCC = 10V to 20V

= 0V or 5V

IN

RDT = 0

4 www.irf.com

Functional Block Diagrams

IR2109

IN

VSS/COM

LEVEL

SHIFT

PULSE

GENERATOR

HV

LEVEL

SHIFTER

PULSE
FILTER

UV

DETECT

IR2109(4)

VB

R

Q

R
S

HO

VS

(S)

SD

DT

SD

VCC

LO

COM

+5V

DEADTIME

VSS/COM

LEVEL

SHIFT

DELAY

UV

DETECT

VB

UV

PULSE

FILTER

DETECT

DETECT

R

Q

R
S

HO

VS

VCC

UV

LO

COM

IR21094

HV

LEVEL

IN

DEADTIME

+5V

VSS/COM

LEVEL
SHIFT

VSS/COM

LEVEL
SHIFT

PULSE

GENERATOR

SHIFTER

DELAY

VSS

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)

(

IR2109(4)

S

Lead Definitions

Symbol Description

IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM

for IR2109 and VSS for IR21094)

SD

Logic input for shutdown (referenced to
DT Programmable dead-time lead, referenced to VSS. (IR21094 only)
VSS Logic Ground (21094 only)
V

B

High side floating supply
HO High side gate drive output
V

S

V

CC

High side floating supply return

Low side and logic fixed supply
LO L ow side gate drive output
COM Low side return

COM for IR2109 and VSS for IR21094)

Lead Assignments

1

V

CC

2

IN

3

SD

4

COM

V

HO

V
LO

8

B

7
6

S

5

1

V

2

IN

3

SD

4

COM

8 Lead PDIP 8 Lead SOIC

IR2109 IR2109S

V

HO

V

14

13

B

12
11

S

10

9
8

V

1

CC

IN

2

SD

3

DT

4

VSS

5

COM

6

LO

7

14 Lead PDIP 14 Lead SOIC

V

1

IN

2

SD

3

DT

4

VSS

5

COM

6

LO

7

IR21094 IR21094S

CC

CC

V

HO

V
LO

V

HO

V

8

B

7
6

S

5

14

13

B

12
11

S

10

9
8

6 www.irf.com

Case Outlines

8 Lead PDIP

IR2109(4)

01-6014

01-3003 01

(MS-001AB)

(S)

A

87

6

E

e

6X

0.25 [.010] C A B

NOTES :

1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.

2. CONTROLLING DIMENSION: MILLIMETER

3. DIMENS IONS ARE SHOWN IN MILL IMET E RS [INCHES].

4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.

D B

5

65

4312

e1

8X b

A1

H

0.25 [.010] A

A

C

0.10 [.004]

6.46 [.255]

3X 1.27 [.050]

y

8 Lead SOIC

DIM

FOOTPRINT

8X 0.72 [.028]

8X 1.78 [.070]

MIN MAX

.0532

A

.0040

A1

.013

b
c .0075 .0098 0.19 0 .25

.189

D

.1497

E

.050 BASIC

e

.025 BASIC 0.635 BASIC

e1

.2284

H

.0099

K

.016

L

0°

y

K x 45 °

8X L

8X c

7

5 DIMENS ION DOES NOT INCLUDE MOLD PR OTRUS IONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].

6 DIMENS ION DOES NOT INCLUDE MOLD PR OTRUS IONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].

7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.

01-0021 11

.0688
.0098
.020

.1968
.1574

.2440
.0196
.050

8°

MILLIMETERSINCHES

MIN MAX

1.35

1.75

0.10

0.25

0.33

0.51

4.80

5.00

3.80

4.00

1.27 BASIC

5.80

6.20

0.25

0.50

0.40

1.27

0°

8°

01-6027

(MS-012AA)

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IR2109(4)

)

(

S

01-6010

14 Lead PDIP

01-3002 03

(MS-001AC)

14 Lead SOIC (narrow body)

8 www.irf.com

01-3063 00

01-6019

(MS-012AB)

IR2109(4)

(S)

IN

SD

HO

LO

IN

IN

LO
HO

(LO)

(HO)

t

on

50%

t

r

50%

t

off

90% 90%

10% 10%

Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions

SD

50%

t

sd

HO

90%

LO

Figure 3. Shutdown Waveform Definitions

IN

(LO)

50% 50%

IN

(HO)

HO

LO

IN

HO

LO

50% 50%

90%

DT

LO-HO

MDT=

90%

DT

10%

LO-HO

- DT

DT

HO-LO

HO-LO

10%

Figure 4. Deadtime Waveform Definitions

t

f

10%

MT

90%

MT

HOLO

Figure 5. Delay Matching Waveform Definitions

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: [phone]

Data and specifications subject to change without notice. 5/18/2001

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