Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
•
Undervoltage lockout for both channels
•
3.3V, 5V and 15V input logic compatible
•
Cross-conduction prevention logic
•
Matched propagation delay for both channels
•
High side output in phase with HIN input
•
Low side output out of phase with
•
Logic and power ground +/- 5V offset.
•
Internal 540ns dead-time, and
•
LIN
input
programmable up to 5us with one
external R
Lower di/dt gate driver for better
•
resistor (IR21084)
DT
noise immunity
Available in Lead-Free
•
Description
The IR2108(4)(S) are high voltage, high speed
power MOSFET and IGBT drivers with dependent high and low side referenced output
channels. Proprietary HVIC and latch immune
CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS
or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for
minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or
IGBT in the high side configuration which operates up to 600 volts.
Typical Connection
up to 600V
V
CC
V
V
CC
HIN
LIN
(Refer to Lead Assignments for correct pin
configuration). This/These diagram(s) show
electrical connections only. Please refer to our
Application Notes and DesignTips for proper
circuit board layout.
HIN
LIN
www.irf.com1
B
HO
V
S
LOCOM
IR2108
V
HIN
LIN
V
TO
LOAD
up to 600V
HO
V
V
CC
CC
SS
HIN
LIN
DT
V
R
DT
B
V
S
COM
SS
LO
IR21084
TO
LOAD
Page 2
IR2108(4)
(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
SymbolDefinitionMin.Max.Units
V
B
V
S
V
HO
V
CC
V
LO
DTProgrammable dead-time pin voltage (IR21084 only)VSS - 0.3V
V
IN
V
SS
dVS/dtAllowable offset supply voltage transient—50V/ns
P
D
Rth
JA
T
J
T
S
T
L
High side floating absolute voltage-0.3625
High side floating supply offset voltageVB - 25VB + 0.3
High side floating output voltageVS - 0.3V
B
+ 0.3
Low side and logic fixed supply voltage-0.325
Low side output voltage-0.3VCC + 0.3
+ 0.3
CC
Logic input voltage (HIN & LIN)V
Logic ground (IR21084 only)V
- 0.3V
SS
- 25V
CC
CC
CC
+ 0.3
+ 0.3
V
Package power dissipation @ TA ≤ +25°C(8 lead PDIP)—1.0
(8 lead SOIC)—0.625
(14 lead PDIP)—1.6
W
(14 lead SOIC)—1.0
Thermal resistance, junction to ambient(8 lead PDIP)—125
(8 lead SOIC)—200
(14 lead PDIP)—75
°C/W
(14 lead SOIC)—120
Junction temperature—150
Storage temperature-50150
°C
Lead temperature (soldering, 10 seconds)—300
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential.
SymbolDefinitionMin.Max.Units
VBHigh side floating supply absolute voltageVS + 10VS + 20
V
S
V
HO
V
CC
V
LO
V
IN
DTProgrammable dead-time pin voltage (IR21084 only)V
V
SS
T
A
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
SymbolDefinition Min. Typ.Max. Units Test Conditions
t
on
t
off
MTDelay matching | ton - t
t
t
DTDeadtime: LO turn-off to HO turn-on(DT
MDTDeadtime matching = | DT
Turn-on propagation delay—220300VS = 0V
Turn-off propagation delay—200280VS = 0V or 600V
off
|
Turn-on rise time—150220VS = 0V
r
Turn-off fall time—5080VS = 0V
f
LO-HO) &
HO turn-off to LO turn-on (DT
LO-HO
- DT
HO-LO)
HO-LO
—0 30
nsec
400540680RDT= 0
456usec RDT = 200k (IR21084)
—060 RDT=0
|
—0600 RDT = 200k (IR21084)
nsec
Static Electrical Characteristics
V
(VCC, VBS) = 15V, VSS = COM, DT= VSS and TA = 25°C unless otherwise specified. The VIL, VIH and I
BIAS
parameters are referenced to VSS/COM and are applicable to the respective input leads: HIN and LIN. The VO, IO and Ron
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
SymbolDefinitionMin. Typ. Max. Units Test Conditions
V
IH
V
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+VCC
V
BSUV+
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
O+
I
O-
Logic “1” input voltage for HIN & logic “0” for LIN2.9——VCC = 10V to 20V
Logic “0” input voltage for HIN & logic “1” for LIN——0.8VCC = 10V to 20V
IL
High level output voltage, V
Low level output voltage, V
Offset supply leakage current——50VB = VS = 600V
Quiescent VBS supply current2075130V
Quiescent VCC supply current0.41.01.6mAVIN = 0V or 5V
Logic “1” input bias current—520HIN = 5V, LIN = 0V
Logic “0” input bias current——2HIN = 0V, LIN = 5V
and VBS supply undervoltage positive going8.08.99.8
threshold
VCC and V
threshold
Hysteresis0.30.7—
Output high short circuit pulsed current120200—VO = 0V,
Output low short circuit pulsed current250350—VO = 15V,
supply undervoltage negative going7.48.29.0
BS
BIAS
O
- V
O
—0.81.4IO = 20 mA
—0.30.6IO = 20 mA
V
µA
µA
V
mA
IN
= 0V or 5V
IN
RDT=0
PW ≤ 10 µs
PW ≤ 10 µs
www.irf.com3
Page 4
IR2108(4)
(S) & (PbF)
Functional Block Diagram
2108
HIN
VSS/COM
LEVEL
SHIFT
PULSE
GENERATOR
HV
LEVEL
SHIFTER
PULSE
FILTER
UV
DETECT
VB
R
Q
R
S
HO
VS
LIN
HIN
DT
LIN
DT
+5V
+5V
VSS
DEADTIME &
SHOOT-THROUGH
PREVENTION
21084
DEADTIME &
SHOOT-THROUGH
PREVENTION
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
PULSE
GENERATOR
DELAY
DELAY
HV
LEVEL
SHIFTER
PULSE
FILTER
DETECT
UV
DETECT
DETECT
VCC
UV
LO
COM
VB
R
Q
R
S
HO
VS
VCC
UV
LO
COM
VSS
4www.irf.com
Page 5
IR2108(4)
(S) & (PbF)
Lead Definitions
Symbol Description
HINLogic input for high side gate driver output (HO), in phase (referenced to COM for IR2108 and
VSS for IR21084)
LIN
DTProgrammable dead-time lead, referenced to VSS. (IR21084 only)
VSSLogic Ground (21084 only)
V
B
HOHigh side gate driver output
V
S
V
CC
LOLow side gate driver output
COMLow side return
Logic input for low side gate driver output (LO), out of phase (referenced to COM for IR2108
and VSS for IR21084)
High side floating supply
High side floating supply return
Low side and logic fixed supply
Lead Assignments
V
1
CC
HIN
2
LIN
3
COM
4
V
HO
V
LO
8
B
7
6
S
5
V
1
CC
HIN
2
LIN
3
COM
4
8 Lead PDIP8 Lead SOIC
IR2108IR2108S
V
HO
V
14
13
B
12
11
S
10
9
8
V
1
CC
HIN
2
LIN
3
DT
4
VSS
5
COM
6
LO
7
14 Lead PDIP14 Lead SOIC
V
1
CC
HIN
2
LIN
3
DT
4
VSS
5
COM
6
LO
7
IR21084IR21084S
V
HO
V
LO
V
HO
V
8
B
7
6
S
5
14
13
B
12
11
S
10
9
8
www.irf.com5
Page 6
IR2108(4)
HIN
LIN
(S) & (PbF)
HO
LO
Figure 1. Input/Output Timing Diagram
HIN
LIN
50%50%
90%
LIN
50%
t
off
90%90%
50%
LO
50%
t
on
t
r
10%10%
50%
HIN
t
on
t
r
90%90%
HO
10%10%
Figure 2. Switching Time Waveform Definitions
t
off
t
f
t
f
HO
LO
DT
LO-HO
MDT=
90%
DT
10%
LO-HO
- DT
DT
HO-LO
HO-LO
10%
Figure 3. Deadtime Waveform Definitions
6www.irf.com
Page 7
IR2108(4)
)
)
(S) & (PbF)
500
400
300
Max .
200
Typ.
100
0
Turn-on Propagation Delay (ns
-50 -250255075 100 125
Temperature (
o
C)
Figure 4A. Turn-on Propagation De lay
vs. Tempe ratur e
500
500
400
Max.
300
Typ.
200
100
0
Turn-on Propagation Delay (ns
101214161820
V
Supply Voltage (V)
BIAS
Figure 4B. Turn-on Propagation Delay
vs. Supply Voltage
500
400
300
Max.
200
Typ.
100
Turn-off Propagation Delay (ns)
0
-50 -250255075 100 125
Temperature (
o
C)
Figure 5A. Turn-off Propagation Delay
vs.Temperature
400
Max.
300
Typ.
200
100
0
Turn-off Propagation Delay (ns)
101214161820
V
Supply V oltage (V )
BIAS
Figure 5B. Turn-off Propagation Delay
vs. Supp ly Voltage
www.irf.com7
Page 8
IR2108(4)
)
)
(S) & (PbF)
500
400
300
Max.
200
100
Turn-on Rise Time (ns
Typ.
0
-50 -250255075 100 125
Temperature (
o
C)
Figure 6A.Turn-on Rise Time
vs. Tem pe ratur e
200
500
400
300
Max .
200
Typ.
100
Turn-on Rise Time (ns
0
101214161820
V
Supply Voltage (V)
BIAS
Figure 6B. Turn-on Rise Time
vs. Supply Voltage
200
150
100
Max.
50
Turn-off Fall Time (ns)
Typ.
0
-50 -250255075100 125
Temperature (
Figure 7A. Turn-off Fall Tim e
vs. Tem perature
o
C)
150
Max .
100
50
Turn-off Fall Time (ns)
Typ.
0
101214161820
Supply Voltage (V)
V
BIAS
Figure 7B. Turn-off Fall Time
vs. Supply Voltage
8www.irf.com
Page 9
IR2108(4)
(S) & (PbF)
1000
800
Max .
600
Typ.
Deadtime (ns)
400
Mi n.
200
-50 -250255075 100 125
o
Temperature (
C)
Figure 8A. Deadtim e vs . Te m perature
7
6
5
Max.
4
3
Deadtime ( s)
2
1
0
050100150200
R
(KΩ)
DT
Typ.
Mi n.
1000
800
Max.
Typ.
600
Deadtime (ns)
Min .
400
200
101214161820
V
Supply Voltage (V)
BIAS
Figure 8B. Deadtime vs. Supply Voltage
8
7
6
5
4
Max.
3
2
Input Voltage (V)
1
0
-50 -250255075100 125
Temperature (
o
C)
Figure 8C. Deadtim e vs. R
(IR21084 Only)
DT
Figure 9A. Logic "1" Input Voltage
vs. Tem pe ratur e
www.irf.com9
Page 10
IR2108(4)
(S) & (PbF)
8
7
6
5
4
Max.
3
2
Input Voltage (V)
1
0
101214161820
V
Supply Voltage (V)
CC
Figure 9B. Logic "1" Input Voltage
vs. Supply Voltage
4.0
4.0
3.2
2.4
1.6
Input Voltage (V)
0.8
Min .
0.0
-50 -250255075100 125
Temperature (
o
Figure 10A. Logic "0" Input Voltage
vs. Tem pe ratur e
4
C)
3.2
3
2.4
2
1.6
Min .
Input Voltage (V)
0.8
0.0
101214161820
V
Supply Voltage (V)
CC
Figure 10B. Logic "0" Input Voltage
vs. Supply Voltage
Max.
1
Typ.
High Level Output Voltage (V)
0
-50-250255075100125
o
Temperature (
C)
Figure 11A. High Level Output
vs. Tem peratur e
10www.irf.com
Page 11
IR2108(4)
)
(S) & (PbF)
4
3
2
Max .
1
Typ.
High Level Output Voltage (V
0
101214161820
V
Supply Voltage (V)
CC
Figure 11B. High Level Output
vs. Supply Voltage
1.5
1.5
1.2
0.9
0.6
Max.
0.3
Typ.
Low Level Output Voltage (V)
0
-50-250255075100 125
o
Temperature (
C)
Figure 12A. Low Level Output
vs. T e m peratur e
500
1.2
0.9
Max.
0.6
Typ.
0.3
Low Level Output Voltage (V)
0
101214161820
V
Supply Voltage (V)
CC
Figure 12B. Low Level Output
vs. Supply Voltage
400
300
200
100
Max.
0
Offset Supply Leakage Current ( A)
-50 -250255075100 125
o
Temperature (
C)
Figure 13A. Offset Supply Leakage Current
vs. Temperature
www.irf.com11
Page 12
IR2108(4)
(S) & (PbF)
500
400
300
200
100
Max.
0
Offset Supply Leakage Current ( A)
0100200300400500600
V
Boost Voltage (V )
B
Figure 13B. Offset Supply Leakage Curre nt
vs. Tem pe ratur e
400
400
300
200
Supply Current ( A)
V
Max .
100
BS
Typ.
Mi n .
0
-50 -250255075100 125
o
Temperature (
C)
Figure 14A. VBS Supply Current
vs. Tem pe ratur e
3.0
300
2.5
2.0
Max.
200
Max.
Supply Current ( A)
100
BS
Typ.
V
Mi n .
0
101214161820
Supply Voltage (V)
V
BS
Figure 14B. VBS Supply Current
vs. Supply Voltage
1.5
Typ.
1.0
Min .
0.5
Vcc Supply Current (mA)
0.0
-50 -250255075100 125
Temperature (
o
C)
Figure 15A. VCC Supply Current
vs. Tempe ratur e
12www.irf.com
Page 13
IR2108(4)
(S) & (PbF)
3.0
2.5
2.0
1.5
Max.
1.0
Supply Current (mA)
V
Typ.
CC
0.5
Min .
0.0
101214161820
Supply Voltage (V)
V
CC
Figure 15B. VCC Supply Current
vs. Supply Voltage
60
60
50
40
30
20
Max.
10
Logic "1" Input Current ( A)
Typ.
0
-50-250255075100 125
Temperature (
o
C)
Figure 16A. Logic "1" Input Current
vs. Tem perature
5
50
40
30
Max.
20
10
Logic "1" Input Current ( A)
Typ.
0
101214161820
Supply Voltage (V )
V
CC
Figure 16B. Logic "1" Input Current
vs. Supply Voltage
4
3
Max.
2
1
Logic "0" Input Current ( A)
0
-50-250255075100 125
Temperatur e (
o
C)
Figure 17A. Logic "0" Input Current
vs. Tem pe r atur e
www.irf.com13
Page 14
IR2108(4)
(S) & (PbF)
5
4
3
Max.
2
1
Logic "0" Input Current ( A)
0
101214161820
Supply Voltage (V)
V
CC
Figure 17B. Logic "0" Input Current
vs. Supply Voltage
11
12
11
10
Max.
Typ.
9
UVLO Threshold (+) (V)
CC
V
Mi n.
8
7
-50-250255075100 125
o
Temperature (
C)
Figure 18. VCC Undervoltage Threshold (+)
vs. Te m pe ratur e
12
10
Max .
9
Typ.
8
Mi n.
7
VCC UVLO Threshold (-) (V)
6
-50-250 255075100125
Temperature (
o
C)
Figure 19. VCC Undervoltage Threshold (-)
vs. Tempe ratur e
11
10
Max.
Typ.
9
UVLO Threshold (+) (V)
V
Min .
8
BS
7
-50-250255075100 125
o
Temperature (
C)
Figure 20. VBS Undervoltage Threshold (+)
vs. Te m pe ratur e
14www.irf.com
Page 15
IR2108(4)
)
(S) & (PbF)
11
10
Max.
9
Typ.
8
Min.
7
UVLO Threshold (-) (V)
BS
V
6
-50 -250255075100 125
o
Temperature (
C)
Figure 21. VBS Undervoltage Threshold (-)
vs. Tempe rature
500
500
400
300
Typ.
200
Min .
100
Output Source Current ( A)
0
-50-250255075100 125
o
Temperature (
C)
Figure 22A. Output Source Current
vs. Temperature
600
400
500
Typ.
400
300
200
Typ.
Output Source Current ( A)
100
Min .
Output Sink Current (mA
0
101214161820
Supply Voltage (V)
V
BIAS
Figure 22B. Output Source Current
vs. Supply Voltage
www.irf.com15
Min .
300
200
100
0
-50-250255075100 125
Temperature (
o
C)
Figure 23A. Output Sink Current
vs. Te m perature
Page 16
IR2108(4)
(S) & (PbF)
600
500
400
300
Typ.
200
Min.
100
Output Sink Current ( A)
0
101214161820
V
Supply Voltage (V)
BIAS
Figure 23B. Output Sink Curr ent
vs. Supply Vo ltage
0
-2
Typ.
-4
-6
-8
Offset Supply Voltage (V)
S
V
-10
101214161820
V
Flouting Supply Voltage (V)
BS
Figure 24. Maximum Vs Ne g ative Off s et
vs. Supply Voltage
140
120
C)
o
100
80
60
Temprature (
40
20
1101001000
Frequency (KHz)
Figure 25. IR2108 vs. Fre quency (IRFBC20),
=33:, VCC=15V
R
gate
140V
70V
0V
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Fig ure 26. IR2108 vs. Fr equency ( IRFB C30),
R
=22:, VCC=15V
gate
140V
70V
0V
16www.irf.com
Page 17
IR2108(4)
(S) & (PbF)
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 27. IR2108 vs. Freque ncy (IRFBC40),
=15:, VCC=15V
R
gate
140
140V
70V
0V
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 28. IR2108 vs. Fre quency (IRFPE50),
=10:, VCC=15V
R
gate
140
1 40V 70 V
0V
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 29. IR21084 vs. Frequency (IRFBC20),
R
=33:, VCC=15V
gate
140V
70V
0V
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 30. IR21084 vs. Fre quency (IRFBC30),
=22:, VCC=15V
R
gate
1 40V
70V
0V
www.irf.com17
Page 18
IR2108(4)
g
0V
(S) & (PbF)
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 31. IR21084 vs. Fre quency (IRFBC40),
=15:, VCC=15V
R
gate
140V
70V
0V
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 32. IR21084 vs. Frequency (IRFPE50),
R
=10:, VCC=15V
ate
1 4
70V
0V
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 33. IR2108S vs. Freque ncy ( IRFBC20),
=33:, VCC=15V
R
gate
1 40V
70V
0V
140
120
C)
100
o
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 34. IR2108S vs. Frequency ( IRFBC30),
=22:, VCC=15V
R
gate
140V
70V
0V
18www.irf.com
Page 19
IR2108(4)
g
(S) & (PbF)
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 35. IR2108S vs. Frequency ( IRFBC40),
=15:, VCC=15V
R
gate
140
140V 70V
0V
140
120
C)
o
100
80
60
Tempreture (
40
20
1101001000
Frequency (KHz )
Figure 36. IR2108S vs. Frequency
(IRFPE50), R
=10:, VCC=15V
ate
140
140V 70V 0V
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 37. IR21084S vs. Frequency (IRFBC20),
R
=33:, VCC=15V
gate
140V
70V
0V
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figu re 38. IR21084S vs. Freq uency (IRF BC30),
R
=22:, VCC=15V
gate
140V
70V
0V
www.irf.com19
Page 20
IR2108(4)
0V
(S) & (PbF)
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 39. IR21084S vs. Freque ncy ( IRFBC40),
=15:, VCC=15V
R
gate
1 40V
70V
0V
140
120
C)
o
100
80
60
Temperature (
40
20
1101001000
Frequency (KHz)
Figure 40. IR21084S vs. Frequency ( IRFPE50),
R
=10:, VCC=15V
gate
1 40V 7
0V
20www.irf.com
Page 21
Case outlines
IR2108(4)
(S) & (PbF)
A
87
6
E
e
6X
8X b
0.25 [.010] C A B
NOT ES :
1. DIMENS IONING & TOLER ANCING PER ASME Y14.5M-1994.
2. CONT ROLL ING DIME NSI ON: MIL LIME TE R
3. DIMENS IONS ARE S HOWN IN MILLIMETE RS [INCHES ].
4. OUT LINE CONFORMS T O JEDE C OUTL INE MS-012AA.
DB
5
65
4312
e1
A1
H
0.25 [.010] A
A
C
0.10 [ .004]
8-Lead PDIP
6.46 [.255]
3X 1.27 [.050]
y
8-Lead SOIC
01-3003 01
DIM
FOOTPRINT
8X 0.72 [.028]
8X 1.78 [.070]
MINMAX
A
.0532
A1
b
c .0075 .00 98 0.190.25
D
E
e
e1
H
K
L
y
.0688
.0040
.0098
.013
.020
.189
.1968
.1497
.1574
.050 B AS IC
.025 B AS IC0. 635 BAS IC
.2284
.2440
.0099
.0196
.016
.050
0°
8°
K x 45°
8X L
8X c
7
5 DIME NSI ON DOES NOT INCL UDE MOLD P ROTR US IONS.
MOLD PROTRU SIONS NOT T O EXCEED 0.15 [.006].
6 DIME NSI ON DOES NOT INCL UDE MOLD P ROTR US IONS.
MOLD PROTRU SIONS NOT T O EXCEED 0.25 [.010].
7 DIME NSI ON IS T HE LE NGT H OF L EAD FOR S OLDE RING T O
A S UBS TRATE .