Datasheet IR2106 4-S Datasheet (IOR)

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Data Sheet No. PD60193

IR21093

(S)

HALF-BRIDGE DRIVER

Features

Floating channel designed for bootstrap operation

•

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V

•

Undervoltage lockout for both channels

•

3.3V, 5V and 15V input logic compatible

•

Cross-conduction prevention logic

•

Matched propagation delay for both channels

•

High side output in phase with IN input

•

Logic and power ground +/- 5V offset

•

Internal 540ns dead-time

•

Lower di/dt gate driver for better noise immunity

•

Description

The IR21093(S) are high voltage, high speed power
MOSFET and IGBT drivers with dependent high and
low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rugge­dized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output,
down to 3.3V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

Product Summary

V

OFFSET

IO+/- 120 mA / 250 mA

V

OUT

t

(typ.) 750 & 200 ns

on/off

Dead Time 540 ns

600V max.

Packages

8-Lead PDIP

10 - 20V

8-Lead SOIC

Typical Connection

up to 600V

V

CC

V

CC

IN

(Refer to Lead Assignments for correct configuration). This/These diagr am(s) show electrical connections only. Please ref er to our
Application Notes and DesignTips for proper circuit board layout.

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IN
COM

LO

V

HO

V

B

TO

S

IR21093

LOAD

)

(

IR21093

S

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

dVS/dt Allowable offset supply voltage transient — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High side floating absolute voltage -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V
Low side and logic fixed supply voltage -0.3 25
Low side output voltage -0.3 VCC + 0.3
Logic input voltage VSS - 0.3 V

Package power dissipation @ TA ≤ +25°C (8 Lead PDIP) — 1.0

(8 Lead SOIC) — 0.625

Thermal resistance, junction to ambient (8 Lead PDIP) — 125

(8 Lead SOIC) — 200
Junction temperature — 150
Storage temperature -50 150
Lead temperature (soldering, 10 seconds) — 300

CC

B

+ 0.3

+ 0.3

W

°C/W

°C

V

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.

Symbol Definition Min. Max. Units

VB High side floating supply absolute voltage VS + 10 VS + 20

V

S

V

HO

V

CC

V

LO

V

IN

T

A

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).

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High side floating supply offset voltage Note 1 600
High side floating output voltage V
Low side and logic fixed supply voltage 10 20
Low side output voltage 0 V
Logic input voltage V
Ambient temperature -40 125 °C

S

SS

V

B

CC

V

CC

V

IR21093

(S)

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15V, CL = 1000 pF, and TA = 25°C, unless otherwise specified.

BIAS

Symbol Definition Min. Typ. Max. Units Test Conditions

t

on

t

off

MT Delay matching, HS & LS turn-on/off — 0 70

t
t

DT Deadtime: LO turn-off to HO turn-on(DT

MDT Deadtime matching = DT

Turn-on propagation delay — 750 950 VS = 0V
Turn-off propagation delay — 200 280 VS = 0V or 600V

Turn-on rise time — 150 220 VS = 0V

r

Turn-off fall time — 50 80 VS = 0V

f

LO-HO) &

HO turn-off to LO turn-on (DT

LO - HO

- DT

HO-LO

HO-LO)

400 540 680
—060

nsec

Static Electrical Characteristics

V

(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to COM

BIAS

and are applicable to the respective input leads. The VO, IO and Ron parameters are referenced to COM and are applicable to
the respective output leads: HO and LO.

Symbol Definition Min. T yp. Max. Units Test Conditions

V

IH

V

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

V

CCUV+

V

BSUV+

V

CCUV-

V

BSUV-

V

CCUVH

V

BSUVH

I

O+

I

O-

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Logic “1” input voltage for HO & logic “0” for LO 2.9 — — VCC = 10V to 20V
Logic “0” input voltage for HO & logic “1” for LO — — 0 .8 VCC = 10V to 20V

IL

High level output voltage, V
Low level output voltage, V
Offset supply leakage current — — 50 VB = VS = 600V
Quiescent VBS supply current 20 60 150 V
Quiescent VCC supply current 0.4 1.0 1.6 mA VIN = 0V or 5V

Logic “1” input bias current — 5 20 IN = 5V, SD = 0V
Logic “0” input bias current — 1 2 IN = 0V, SD = 5V
VCC and V
threshold
VCC and VBS supply undervoltage negative going 7. 4 8. 2 9 .0
threshold
Hysteresis 0.3 0.7 —

Output high short circuit pulsed vurrent 120 200 — VO = 0V, PW ≤ 10 µs
Output low short circuit pulsed current 250 350 — VO = 15V ,PW ≤ 10 µs

supply undervoltage positive going 8 .0 8 .9 9.8

BS

BIAS

O

- V

O

— 0.8 1.4 IO = 20 mA
— 0.3 0.6 IO = 20 mA

V

µA

µA

V

mA

= 0V or 5V

IN

RDT = 0

)

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IR21093

S

Functional Block Diagrams

IR21093

IN

VSS/COM

LEVEL

SHIFT

PULSE

GENERATOR

HV

LEVEL

SHIFTER

PULSE

FILTER

UV

DETECT

VB

R

Q

R
S

HO

VS

DEADTIME

VSS/COM

LEVEL

SHIFT

DELAY

UV

DETECT

VCC

LO

COM

Lead Definitions

Symbol Description

IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM)
V

B

HO High side gate drive output
V

S

V

CC

LO L ow side gate drive output
COM Low side return

High side floating supply

High side floating supply return
Low side and logic fixed supply

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Lead Assignments

IR21093

(S)

1

V

CC

2

IN

3

COM

4

LO

V

HO

V

8

B

7
6

S

5

1

V

CC

2

IN

3

COM

4

LO

V

HO

V

B

S

8-Lead PDIP 8-Lead SOIC

IR21093 IR21093S

(LO)

IN

IN

HO

LO

IN

LO
HO

(HO)

50%

t

on

t

r

10% 10%

Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions

IN

(LO)

50% 50%

IN

IN

50% 50%

(HO)

50%

t

off

90% 90%

8

7
6

5

t

f

HO

10%

MT

90%

HO

LO

DT
90%

10%

90%

10%

DT

LO

MT

HOLO

Figure 3. Deadtime Waveform Definitions Figure 4. Delay Matching Waveform Definitions

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IR21093

Case Outlines

)

(

S

01-6014

8 Lead PDIP

01-3003 01

(MS-001AB)

A

87

6

E

e

6X

8X b

0.25 [.010] C A B

NOTES :

1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.

2. CONTROLLING DIMENSION : MILLIMETER

3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES].

4. OUTLINE CONF ORMS TO JEDEC OUTLINE MS-012AA.

D B

5

65

4312

e1

A1

H

0.25 [.010] A

A

C

0.10 [.004]

6.46 [.255]

3X 1.27 [.050]

y

8 Lead SOIC

DIM

FOOTPRINT

8X 0.72 [.028]

8X 1.78 [.070]

MIN MAX

.0532

A

.0040

A1

.013

b
c .0075 .0098 0.19 0 .25

.189

D

.1497

E

.050 BASIC

e

.025 BASIC 0.635 BASIC

e1

.2284

H

.0099

K

.016

L

0°

y

K x 45°

8X L

8X c

7

5 DIMENS ION DOES NOT INCLUDE MOLD PR OTRUS IONS .
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].

6 DIMENS ION DOES NOT INCLUDE MOLD PR OTRUS IONS .
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].

7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A S UBSTRATE.

01-0021 11

.0688
.0098
.020

.1968
.1574

.2440
.0196
.050

8°

MILLIMET ERSINCHES

MIN MAX

1.35

1.75

0.10

0.25

0.33

0.51

4.80

5.00

3.80

4.00

1.27 BASIC

5.80

6.20

0.25

0.50

0.40

1.27

0°

8°

01-6027

(MS-012AA)

7/9/2001

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