Datasheet IR2101S, IR2101 Datasheet (International Rectifier)

Data Sheet No. PD-6.043C

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IR2101

HIGH AND LOW SIDE DRIVER

Features

n Floating channel designed for bootstrap operation

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune

n Gate drive supply range from 10 to 20V
n Undervoltage lockout
n 5V Schmitt-triggered input logic
n Matched propagation delay for both channels

n Outputs in phase with inputs

Description

The IR2101 is a high voltage, high speed power
MOSFET and IGBT driver with independent high and
low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rugge­dized monolithic construction. The logic input is com­patible with standard CMOS or LSTTL outputs. The
output drivers feature a high pulse current buff er stage
designed for minimum driver cross-conduction. The
floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high side configura­tion which operates up to 600 volts.

Product Summary

V

OFFSET

IO+/- 100 mA / 210 mA

V

OUT

t

(typ.) 130 & 90 ns

on/off

Delay Matching 30 ns

600V max.

10 - 20V

Packages

Typical Connection

V

CC

HIN

LIN

V

CC

HIN
LIN

V

HO

V

LOCOM

up to 600V

B

S

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-1

TO

LOAD

IR2101

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Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.

Parameter Value

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

dVs/dt Allowable Offset Supply Voltage Transient — 50 V/ns

P

D

R

θJA

T

J

T

S

T

L

High Side Floating Supply Voltage -0.3 625
High Side Floating Supply Offset Voltage VB - 25 VB + 0.3
High Side Floating Output Voltage VS - 0.3 V
Low Side and Logic Fixed Supply Voltage -0.3 25
Low Side Output Voltage -0.3 VCC + 0.3
Logic Input Voltage (HIN & LIN) -0.3 V

Package Power Dissipation @ TA ≤ +25°C (8 Lead DIP) — 1.0

(8 Lead SOIC) — 0.625

Thermal Resistance, Junction to Ambient (8 Lead DIP) — 125

(8 Lead SOIC) — 200
Junction Temperature — 15 0
Storage Temperature -55 150 °C
Lead Temperature (Soldering, 10 seconds) — 300

CC

B

+ 0.3

+ 0.3

°C/W

V

W

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

T

A

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS.

High Side Floating Supply Absolute Voltage VS + 10 VS + 20
High Side Floating Supply Offset Voltage Note 1 600
High Side Floating Output Voltage V
Low Side and Logic Fixed Supply Voltage 10 20
Low Side Output Voltage 0 V
Logic Input Voltage (HIN & LIN) 0 V

Ambient Temperature -40 125

B-2 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

offset rating is tested with all supplies biased at 15V differential.

S

Pa rameter Value

S

V

B

CC
CC

V

°C

IR2101

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Dynamic Electrical Characteristics

V

(VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified .

BIAS

Parameter Value

Symbol Definition Min. T yp. Max. Units Test Conditions

t

on

t

off

t
t

MT Dela y Matching, HS & LS Turn-On/Off — 30 —

Static Electrical Characteristics

V

(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are ref erenced to COM.

BIAS

The V

O

Symbol Definition Min. Typ. Max. Units Test Conditions

V
V

V

OH

V

OL

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

V

CCUV+

V

CCUV -

I

O+

I

O-

T urn-On Propagation Delay — 13 0 200 VS = 0V
T urn-Off Propagation Dela y — 90 200 VS = 600V
T urn-On Rise Time — 80 1 20 ns

r

Turn-Off Fall Time — 40 70

f

and IO parameters are referenced to COM and are applicable to the respectiv e output leads: HO or LO .

Par ameter Value

Logic “1” Input Voltage 2.7 — — VCC = 10V to 20V

IH

Logic “0” Input Voltage — — 0.8 VCC = 10V to 20V

IL

High Level Output Voltage, V
Low Le vel Output Voltage, V
Offset Supply Leakage Current — — 50 VB = VS = 600V
Quiescent VBS Supply Current — 20 50 V
Quiescent VCC Supply Current — 140 2 40 µA VIN = 0V or 5V
Logic “1” Input Bias Current — 20 40 VIN = 5V
Logic “0” Input Bias Current — — 1.0 V
VCC Supply Undervoltage Positiv e Going 8.8 9.3 9.8

Threshold
VCC Supply Undervoltage Negative Going 7.5 8.2 8.6

Threshold
Output High Short Circuit Pulsed Current 10 0 125 — VO = 0V , V

Output Low Short Circuit Pulsed Current 21 0 250 — VO = 15V , V

BIAS

O

- V

O

— — 100 IO = 0A
— — 100 IO = 0A

V

mV

V

mA

= 0V or 5V

IN

= 0V

IN

IN

PW ≤ 10 µs

IN

PW ≤ 10 µs

= 5V

= 0V

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-3

IR2101

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Functional Block Diagram

HIN

UV

DETECT

PULSE

GEN

HV

LEVEL

SHIFT

PULSE
FILTER

V

B

Q

R
S

HO

V

V

S

CC

LIN

Lead Definitions

Lead

Symbol Description

HIN Logic input for high side gate driver output (HO), in phase
LIN Logic input for low side gate driver output (LO), in phase
V

B

HO High side gate drive output
V

S

V

CC

LO Low side gate drive output
COM Low side return

High side floating supply

High side floating supply return
Low side and logic fixed supply

Lead Assignments

LO

COM

8 Lead DIP SO-8

B-4 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

IR2101 IR2101S

Device Information

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Process & Design Rule HVDCMOS 4.0 µm
Transistor Count 168
Die Size 67 X 91 X 26 (mil)
Die Outline

Thickness of Gate Oxide 800Å
Connections Material Poly Silicon

Contact Hole Dimension 5 µm X 5 µm
Insulation Layer Material PSG (SiO2)

Passivation Material PSG (SiO2)

Method of Saw Full Cut
Method of Die Bond Ablebond 84 - 1
Wire Bond Method Thermo Sonic

Leadframe Material Cu

Pa ckage Types 8 Lead PDIP / SO-8

Remarks:

IR2101

First Width 4 µm
Layer Spacing 6 µm

Thickness 5000Å

Material Al - Si (Si: 1.0% ±0.1%)
Second Width 6 µm
Layer Spacing 9 µm

Thickness 20,000Å

Thickness 1.5 µm

Thickness 1.5 µm

Material Au (1.0 mil / 1.3 mil)

Die Area Ag

Lead Plating Pb : Sn (37 : 63)

Materials EME6300 / MP150 / MP190

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-5

IR2101

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HIN
LIN

HO
LO

Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions

HIN
LIN

Figure 3. Delay Matc hing Waveform Definitions

50%

LO

10%

MT

HIN
LIN

HO
LO

50%

HO

90%

50%

t

on

t

r

10% 10%

MT

HOLO

50%

t

off

90% 90%

t

f

B-6 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL