Page 1
IPD13N03LA
IPU13N03LA
OptiMOS®2 Power-Transistor
Product Summary
Features
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC
1)
for target applications
• N-channel
• Logic level
• Excellent gate charge x R
• Very low on-resistance R
product (FOM)
DS(on)
DS(on)
• Superior thermal resistance
• 175 °C operating temperature
• dv /dt rated
Type Package Ordering Code Marking
V
DS
R
DS(on),max
I
D
25 V
(SMD version) 13
30 A
P-TO251-3-21P-TO252-3-11
mΩ
IPD13N03LA P-TO252-3-11 Q67042-S4159 13N03LA
IPU13N03LA P-TO251-3-21 Q67042-S4160 13N03LA
Maximum ratings, at T
Parameter Symbol Conditions Unit
Continuous drain current
Pulsed drain current
Avalanche energy, single pulse
Reverse diode dv /dt dv /dt
Gate source voltage
Power dissipation
Operating and storage temperature
=25 °C, unless otherwise specified
j
I
D
TC=25 °C
T
I
D,pulse
E
AS
TC=25 °C
ID=24 A, R
I
di /dt =200 A/µs,
T
4)
V
GS
P
tot
T
, T
j
TC=25 °C
stg
2)
=100 °C
C
3)
=25 Ω
GS
=30 A, VDS=20 V,
D
=175 °C
j,max
Value
30 A
30
210
60 mJ
6 kV/µs
±20 V
46 W
-55 ... 175 °C
IEC climatic category; DIN IEC 68-1 55/175/56
1)
J-STD20 and JESD22
Rev. 1.4 page 1 2004-02-04
Page 2
IPD13N03LA
IPU13N03LA
Parameter Symbol Conditions Unit
Values
min. typ. max.
Thermal characteristics
Thermal resistance, junction - case
SMD version, device on PCB
Electrical characteristics, at T
=25 °C, unless otherwise specified
j
R
thJC
R
thJA
minimal footprint - - 75
6 cm
2
cooling area
5)
- - 3.2 K/W
--50
Static characteristics
Drain-source breakdown voltage
Gate threshold voltage
Zero gate voltage drain current
V
(BR)DSSVGS
V
GS(th)
I
DSS
=0 V, ID=1 mA
VDS=VGS, ID=20 µA
VDS=25 V, VGS=0 V,
T
=25 °C
j
25 - - V
1.2 1.6 2
- 0.1 1 µA
V
=25 V, VGS=0 V,
DS
T
=125 °C
j
Gate-source leakage current
Drain-source on-state resistance
I
R
GSS
DS(on)
VGS=20 V, VDS=0 V
VGS=4.5 V, ID=20 A
V
=4.5 V, ID=20 A,
GS
SMD version
V
=10 V, ID=30 A
GS
V
=10 V, ID=30 A,
GS
SMD version
Gate resistance
Transconductance
2)
Current is limited by bondwire; with an R
3)
See figure 3
4)
T
=150 °C and duty cycle D <0.25 for VGS<-5 V
j,max
5)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
R
G
g
thJC
fs
|VDS|>2|ID|R
I
=30 A
D
=3.2 K/W the chip is able to carry 47 A.
DS(on)max
,
- 10 100
- 10 100 nA
- 17.5 21.9
- 17.7 22.1
- 10.8 13.0
- 10.7 12.8
- 0.9 -
18 36 - S
mΩ
Ω
Rev. 1.4 page 2 2004-02-04
Page 3
IPD13N03LA
y
g
IPU13N03LA
Parameter Symbol Conditions Unit
Values
min. typ. max.
namic characteristics
D
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate Char
e Characteristics
Gate to source charge
Gate charge at threshold
C
iss
V
=0 V, VDS=15 V,
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
6)
Q
gs
Q
g(th)
GS
f =1 MHz
V
=15 V, VGS=10 V,
DD
I
=15 A, R
D
=2.7 Ω
G
- 784 1043 pF
- 303 402
-4162
- 5.4 8 ns
- 4.6 7
-1523
- 2.6 3.9
-34nC
- 1.3 1.7
Gate to drain charge
Switching charge
Gate charge total
Gate plateau voltage
Gate charge total, sync. FET
Output charge
Reverse Diode
Diode continous forward current
Diode pulse current
Diode forward voltage
Reverse recovery charge
Q
gd
Q
sw
Q
g
V
plateau
Q
g(sync)
Q
oss
I
S
I
S,pulse
V
SD
Q
rr
V
=15 V, ID=15 A,
DD
V
=0 to 5 V
GS
VDS=0.1 V,
V
=0 to 5 V
GS
VDD=15 V, VGS=0 V
TC=25 °C
VGS=0 V, IF=30 A,
T
=25 °C
j
VR=15 V, IF=IS,
di
/dt =400 A/µs
F
- 1.8 2.7
-35
-68
- 3.4 - V
-67nC
-79
- - 30 A
- - 210
- 0.95 1.2 V
- - 10 nC
6)
See figure 16 for gate charge parameter definition
Rev. 1.4 page 3 2004-02-04
Page 4
1 Power dissipation 2 Drain current
P
=f(TC) ID=f(TC); VGS≥10 V
tot
IPD13N03LA
IPU13N03LA
50
40
40
30
30
[W]
tot
P
[A]
D
I
20
20
10
10
0
0 50 100 150 200
TC [°C]
0
0 50 100 150 200
TC [°C]
3 Safe operation area 4 Max. transient thermal impedance
I
=f(VDS); TC=25 °C; D =0 Z
D
parameter: t
p
1000
1 µs
10 µs
100 µs
[A]
D
I
limited by on-state
resistance
100
DC
10
1 ms
10 ms
1
0.1 1 10 100
VDS [V]
=f(tp)
thJC
parameter: D =tp/T
10
0.5
1
0.2
[K/W]
thJC
Z
0.1
0.05
0.02
0.1
0.01
single pulse
0000001
0.01
10
-6
10
-5
10
10
-3
-4
10
-2
10
-1
10
0
tp [s]
Rev. 1.4 page 4 2004-02-04
Page 5
5 Typ. output characteristics 6 Typ. drain-source on resistance
I
=f(VDS); Tj=25 °C R
D
parameter: V
GS
=f(ID); Tj=25 °C
DS(on)
parameter: V
GS
IPD13N03LA
IPU13N03LA
60
50
10 V
4.5 V
50
40
3 V
3.2 V
3.5 V
3.8 V
40
]
30
Ω
[m
DS(on)
R
20
[A]
D
I
4.1 V
30
3.8 V
20
3.5 V
10
3.2 V
3 V
2.8 V
0
0123
VDS [V]
10
0
0 1020304050
ID [A]
7 Typ. transfer characteristics 8 Typ. forward transconductance
4.1 V
4.5 V
10 V
I
=f(VGS); |VDS|>2|ID|R
D
parameter: T
j
60
40
[A]
D
I
20
0
012345
DS(on)max
175 °C
VGS [V]
25 °C
gfs=f(ID); Tj=25 °C
50
40
30
[S]
fs
g
20
10
0
0 102030405060
ID [A]
Rev. 1.4 page 5 2004-02-04
Page 6
9 Drain-source on-state resistance 10 Typ. gate threshold voltage
IPD13N03LA
IPU13N03LA
R
=f(Tj); ID=30 A; VGS=10 V V
DS(on)
24
20
16
]
Ω
[m
DS(on)
12
98 %
typ
R
8
4
0
-60 -20 20 60 100 140 180
Tj [°C]
=f(Tj); VGS=V
GS(th)
parameter: I
2.5
2
1.5
[V]
GS(th)
V
1
0.5
0
-60 -20 20 60 100 140 180
DS
D
200 µA
20 µA
Tj [°C]
11 Typ. Capacitances 12 Forward characteristics of reverse diode
C =f(V
); VGS=0 V; f =1 MHz IF=f(VSD)
DS
4
10000
10
10
3
1000
Ciss
Coss
[pF]
C
2
100
10
Crss
1
10
10
0 102030
VDS [V]
parameter: T
1000
100
[A]
F
I
10
1
0.0 0.5 1.0 1.5 2.0
j
25 °C
175 °C, 98%
175 °C
25 °C, 98%
VSD [V]
Rev. 1.4 page 6 2004-02-04
Page 7
13 Avalanche characteristics 14 Typ. gate charge
IPD13N03LA
IPU13N03LA
=f(tAV); R
I
AS
parameter: T
100
[A]
10
AV
I
1
1 10 100 1000
GS
j(start)
150 °C
=25 Ω
100 °C
tAV [µs]
25 °C
=f(Q
V
GS
gate
parameter: V
12
10
8
[V]
6
GS
V
4
2
0
02468101214
); ID=25 A pulsed
DD
Q
gate
[nC]
5 V
15 V
20 V
15 Drain-source breakdown voltage 16 Gate charge waveforms
V
=f(Tj); ID=1 mA
BR(DSS)
29
28
27
26
25
[V]
24
BR(DSS)
V
23
22
21
20
-60 -20 20 60 100 140 180
Tj [°C]
V
GS
Q
V
gs(th)
Q
g(th)
Q
gs
g
Q
sw
Q
gd
Q
gate
Rev. 1.4 page 7 2004-02-04
Page 8
Package Outline
P-TO252-3-11: Outline
IPD13N03LA
IPU13N03LA
Footprint: Packaging:
Dimensions in mm
Rev. 1.4 page 8 2004-02-04
Page 9
Package Outline
P-TO251-3-21: Outline
IPD13N03LA
IPU13N03LA
Dimensions in inch [mm]
Rev. 1.4 page 9 2004-02-04
Page 10
IPD13N03LA
©
IPU13N03LA
Published by
Infineon Technologies AG
Bereich Kommunikation
St.-Martin-Straße 53
D-81541 München
Infineon Technologies AG 1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as
warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts started herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices, please contact your
nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide
(see address list).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact your nearest Infineon Technologies office.
Infineon Technologies' components may only be used in life-support devices or systems with the
expressed written approval of Infineon Technologies if a failure of such components can reasonably
be expected to cause the failure of that life-support device or system, or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail,
it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.4 page 10 2004-02-04
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