Datasheet ipd75n04s4-06_ds_1_1 Datasheet

IPD75N04S4-06

OptiMOS®-T2 Power-Transistor

Features

• N-channel - Enhancement mode

• AEC qualified

• MSL1 up to 260°C peak reflow

• 175°C operating temperature

• Green Product (RoHS compliant)

• 100% Avalanche tested

Product Summary

V

DS

R

DS(on),max

I

D

40 V

5.9

75 A

PG-TO252-3-313

mΩ

Type Package Marking

IPD75N04S4-06 PG-TO252-3-313 4N0406

Maximum ratings, at T

Parameter Symbol Conditions Unit

Continuous drain current

Pulsed drain current

Avalanche energy, single pulse

Avalanche current, single pulse

Gate source voltage

Power dissipation

Operating and storage temperature

=25 °C, unless otherwise specified

j

I

D

TC=25°C, VGS=10V

T

1)

I

D,pulse

E

AS

I

AS

V

GS

P

tot

T

, T

j

TC=25°C

ID=35A

-

- ±20 V

TC=25°C

- -55 ... +175 °C

stg

=100°C, VGS=10V

C

2)

53

Value

75 A

300

72 mJ

75 A

58 W

IEC climatic category; DIN IEC 68-1 - - 55/175/56

Rev. 1.1 page 1 2010-07-15

IPD75N04S4-06

Parameter Symbol Conditions Unit

Values

min. typ. max.

Thermal characteristics

Thermal resistance, junction - case

Thermal resistance, junction ambient, leaded

SMD version, device on PCB

Electrical characteristics, at T

1)

R

thJC

R

thJA

R

thJA

=25 °C, unless otherwise specified

j

- - - 2.6 K/W

---62

minimal footprint - - 62

6 cm

2

cooling area

2)

--40

Static characteristics

Drain-source breakdown voltage

Gate threshold voltage

V

(BR)DSSVGS

V

GS(th)

=0V, ID= 1mA

VDS=VGS, ID=26µA

40 - - V

2.0 3.0 4.0

Zero gate voltage drain current

Gate-source leakage current

Drain-source on-state resistance

I

R

DSS

GSS

DS(on)

VDS=40V, VGS=0V, T

=25°C

j

V

=18V, VGS=0V,

DS

=85°C

j

2)

T

VGS=20V, VDS=0V

VGS=10V, ID=75A

- 0.015 1 µA

-120

- - 100 nA

- 5.0 5.9

mΩ

Rev. 1.1 page 2 2010-07-15

IPD75N04S4-06

y

g

Parameter Symbol Conditions Unit

Values

min. typ. max.

namic characteristics

D

Input capacitance

Output capacitance

Reverse transfer capacitance

Turn-on delay time

Rise time

Turn-off delay time

Fall time

Gate Char

e Characteristics

Gate to source charge

Gate to drain charge

Gate charge total

1)

C

iss

V

=0 V, VDS=25 V,

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

1)

Q

gs

Q

gd

Q

g

GS

f =1 MHz

V

=20V, VGS=10V,

DD

I

=75A, R

D

V

DD

V

GS

G

=32V, ID=75A, =0 to 10V

=3.5Ω

- 1960 2550 pF

- 490 640

-1535

-7-ns

-9-

-6-

-8-

- 11.7 15.2 nC

- 3.5 8.1

- 24.5 32

Gate plateau voltage

V

plateau

- 5.9 - V

Reverse Diode

Diode continous forward current

I

S

- - 75 A

1)

TC=25°C

Diode pulse current

1)

Diode forward voltage

Reverse recovery time

Reverse recovery charge

1)

Defined by design. Not subject to production test.

2)

Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain

connection. PCB is vertical in still air.

1)

I

S,pulse

V

SD

t

rr

Q

rr

VGS=0V, IF=75A, T

=25°C

j

VR=20V, IF=50A,

di

/dt =100A/µs

F

- - 300

- 0.9 1.3 V

-36-ns

-31-nC

Rev. 1.1 page 3 2010-07-15

1 Power dissipation 2 Drain current

P

= f(TC); V

tot

≥ 6 V ID = f(TC); V

GS

IPD75N04S4-06

≥ 6 V

60

80

70

50

60

40

50

[W]

30

tot

P

40

[A]

D

I

30

20

10

0

0 50 100 150 200

TC [°C]

0

0 50 100 150 200

TC [°C]

3 Safe operating area 4 Max. transient thermal impedance

I

= f(VDS); TC = 25 °C; D = 0 Z

D

parameter: t

p

1000

1 µs

10 µs

100

[A]

D

I

100 µs

10

1 ms

1

0.1 1 10 100

VDS [V]

= f(tp)

thJC

parameter: D =tp/T

1

10

0.5

0

10

-1

-2

10

0.1

0.05

0.01

single pulse

-6

10

-5

[K/W]

thJC

Z

10

-4

10

-3

10

-2

10

-1

10

0

tp [s]

Rev. 1.1 page 4 2010-07-15

IPD75N04S4-06

5 Typ. output characteristics 6 Typ. drain-source on-state resistance

I

= f(VDS); Tj = 25 °C R

D

parameter: V

GS

parameter: V

= f(ID); Tj = 25 °C

DS(on)

GS

280

14

5.5 V 6 V

240

10 V

12

200

]

Ω

[m

DS(on)

R

10

[A]

D

I

160

120

7 V

6.5 V

8

80

40

0

01234

VDS [V]

6 V

5.5 V

5 V

6

4

0 40 80 120

ID [A]

7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance

I

= f(VGS); V

D

parameter: T

= 6V R

DS

j

= f(Tj); ID = 75 A; V

DS(on)

GS

= 10 V

6.5 V

7 V

10 V

200

150

100

[A]

D

I

50

175 °C

25 °C

-55 °C

0

34567

VGS [V]

9

8

7

]

Ω

[m

6

DS(on)

R

5

4

3

-60 -20 20 60 100 140 180

Tj [°C]

Rev. 1.1 page 5 2010-07-15

IPD75N04S4-06

9 Typ. gate threshold voltage 10 Typ. capacitances

V

GS(th)

= f(Tj); V

parameter: I

4

3.5

3

[V]

GS(th)

V

2.5

2

1.5

-60 -20 20 60 100 140 180

= V

GS

DS

D

150 µA

26 µA

C = f(VDS); V

4

10

3

10

C [pF]

2

10

1

10

= 0 V; f = 1 MHz

GS

Ciss

Coss

Crss

0 5 10 15 20 25 30

Tj [°C]

VDS [V]

11 Typical forward diode characteristicis 12 Avalanche characteristics

IF = f(V

parameter: T

) I

SD

j

3

10

2

10

25 °C

175 °C

[A]

F

I

1

10

0

10

0 0.2 0.4 0.6 0.8 1 1.2 1.4

175 °C

VSD [V]

= f(tAV)

A S

parameter: T

100

10

[A]

AV

I

1

0.1

0.1 1 10 100 1000

j(start)

150 °C

tAV [µs]

25 °C

100 °C

Rev. 1.1 page 6 2010-07-15

IPD75N04S4-06

13 Avalanche energy 14 Drain-source breakdown voltage

E

= f(Tj) V

AS

parameter: I

D

= f(Tj); ID = 1 mA

BR(DSS)

160

17 A

46

44

120

42

[V]

80

[mJ]

AS

E

35 A

40

75 A

0

25 75 125 175

BR(DSS)

V

40

38

36

-55 -15 25 65 105 145

Tj [°C]

15 Typ. gate charge 16 Gate charge waveforms

Tj [°C]

V

= f(Q

GS

gate

parameter: V

10

9

8

7

6

[V]

5

GS

V

4

3

2

1

0

0 5 10 15 20 25 30

); ID = 75 A pulsed

DD

Q

gate

8 V

[nC]

32 V

V

GS

Q

g

V

gs(th)

Q

g(th)

Q

gs

Q

sw

Q

gd

Q

gate

Rev. 1.1 page 7 2010-07-15

IPD75N04S4-06

r

Published by Infineon Technologies AG 81726 Munich, Germany

Legal Disclaime

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Rev. 1.1 page 8 2010-07-15

Revision History

IPD75N04S4-06

Version

Revision 1.0

Revision 1.1

Date

06.04.2010

15.07.2010

Changes

Final Data Sheet

Update of Gate Charge diagram

Rev. 1.1 page 9 2010-07-15