
OptiMOS
TM
3 Power-Transistor
Features
• N-channel, normal level
• Excellent gate charge x R
DS(on)
product (FOM)
• Very low on-resistance R
DS(on)
• 175 °C operating temperature
• Pb-free lead plating; RoHS compliant
• Qualified according to JEDEC
1)
for target application
• Halogen-free according to IEC61249-2-21
• Ideal for high-frequency switching and synchronous rectification
Maximum ratings, at Tj=25 °C, unless otherwise specified
Parameter Symbol Conditions Unit
Continuous drain current
Pulsed drain current
2)
I
D,pulse
TC=25 °C
100
Avalanche energy, single pulse
E
AS
ID=25 A, RGS=25 W
210 mJ
Reverse diode dv/dt dv/dt 10 kV/µs
Operating and storage temperature
IEC climatic category; DIN IEC 68-1 55/175/56
Rev. 2.3 page 1 2011-07-14

IPD600N25N3 G
Parameter Symbol Conditions Unit
min. typ. max.
Thermal characteristics
Thermal resistance, junction - case
R
thJA
minimal footprint - - 75
6 cm2 cooling area
3)
- - 50
Electrical characteristics, at Tj=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V
(BR)DSSVGS
=0 V, ID=1 mA
250 - - V
V
GS(th)
VDS=VGS, ID=90 µA
2 3 4
Zero gate voltage drain current
VDS=200 V, VGS=0 V,
Tj=25 °C
VDS=200 V, VGS=0 V,
Tj=125 °C
- 10 100
Gate-source leakage current
I
GSS
VGS=20 V, VDS=0 V
- 1 100 nA
Drain-source on-state resistance
R
DS(on)
VGS=10 V, ID=25 A
- 51 60
mW
|VDS|>2|ID|R
DS(on)max
,
ID=25 A
Thermal resistance, junction ambient
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
Rev. 2.3 page 2 2011-07-14

IPD600N25N3 G
Parameter Symbol Conditions Unit
min. typ. max.
Reverse transfer capacitance
Gate Charge Characteristics
4)
Q
oss
VDD=100 V, VGS=0 V
- 45 60 nC
Diode continous forward current
I
S
- - 25 A
VGS=0 V, IF=25 A,
Tj=25 °C
- 0.9 1.2 V
Reverse recovery time
4)
See figure 16 for gate charge parameter definition
VR=100 V, IF=12A,
diF/dt=100 A/µs
VGS=0 V, VDS=100 V,
f=1 MHz
VDD=100 V,
VGS=10 V, ID=12 A,
RG=1.6 W
VDD=100 V, ID=12 A,
VGS=0 to 10 V
Rev. 2.3 page 3 2011-07-14

IPD600N25N3 G
1 Power dissipation 2 Drain current
P
tot
=f(TC) ID=f(TC); V
GS
≥10 V
3 Safe operating area 4 Max. transient thermal impedance
ID=f(VDS); TC=25 °C; D=0 Z
thJC
=f(tp)
parameter: t
p
parameter: D=tp/T
0
20
40
60
80
100
120
140
160
0 50 100 150 200
0
10
20
30
0 50 100 150 200
Rev. 2.3 page 4 2011-07-14

IPD600N25N3 G
5 Typ. output characteristics 6 Typ. drain-source on resistance
ID=f(VDS); Tj=25 °C R
DS(on)
=f(ID); Tj=25 °C
parameter: V
GS
parameter: V
GS
7 Typ. transfer characteristics 8 Typ. forward transconductance
ID=f(VGS); |VDS|>2|ID|R
DS(on)max
gfs=f(ID); Tj=25 °C
0
20
40
60
80
100
0 10 20 30
0
10
20
30
40
50
60
70
80
0 25 50 75
0
10
20
30
40
50
60
0 1 2 3 4 5
Rev. 2.3 page 5 2011-07-14

IPD600N25N3 G
9 Drain-source on-state resistance 10 Typ. gate threshold voltage
R
DS(on)
=f(Tj); ID=25 A; VGS=10 V V
GS(th)
=f(Tj); VGS=V
DS
11 Typ. capacitances 12 Forward characteristics of reverse diode
C=f(VDS); VGS=0 V; f=1 MHz IF=f(VSD)
0
20
40
60
80
100
120
140
160
180
200
-60 -20 20 60 100 140 180
0
0.5
1
1.5
2
2.5
3
3.5
4
-60 -20 20 60 100 140 180
Rev. 2.3 page 6 2011-07-14

IPD600N25N3 G
13 Avalanche characteristics 14 Typ. gate charge
IAS=f(tAV); RGS=25 W
VGS=f(Q
gate
); ID=12 A pulsed
parameter: T
j(start)
parameter: V
DD
15 Drain-source breakdown voltage 16 Gate charge waveforms
V
BR(DSS)
=f(Tj); ID=1 mA
220
230
240
250
260
270
280
290
-60 -20 20 60 100 140 180
Rev. 2.3 page 7 2011-07-14

IPD600N25N3 G
PG-TO252-3: Outline
Rev. 2.3 page 8 2011-07-14

IPD600N25N3 G
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
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conditions or characteristics. With respect to any examples or hints given herein, any typical
values stated herein and/or any information regarding the application of the device,
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,
including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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on the types in question, please contact the nearest Infineon Technologies Office.
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Rev. 2.3 page 9 2011-07-14